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Logic: Standard, Special and Programmable
In Brief . . .
This selector guide is a quick reference to Motorola's vast offering of standard logic integrated circuits. In TTL, popular due to its ease of use, low cost, medium-to-high speed operation and good output drive capability, Motorola offers both LS and FAST. Motorola's CMOS portfolio includes MC14000B standard CMOS series devices, High-Speed CMOS consisting of a full line of products that are pinout- compatible with many LSTTL and MC14000B standard CMOS logic devices which offers designers a solution to the long-standing combined barrier -- high speed and low power. Motorola's Emitter Coupled Logic (MECL) is a non-saturated form of digital logic which eliminates transistor storage time permitting very high speed operation. Motorola offers five versions of MECL: MECL 10K, MECL 10H, MECL III, and the recently introduced families ECLinPS (ECL in picoseconds) and ECLinPS Lite. Also included are timing solution products such as clock drivers, clock generators and programmable delay chips, high performance and communications products such as VCO's, prescalers, and synthesizers, and a wide variety of translators, low-voltage bus interface and serial data transmission devices. Field programmable logic and in particular, field programmable arrays, have become the solution of choice for logic design implementation in applications where time to market is a critical product development factor. In addition, reconfigurable arrays have been used to enhance Customer product flexibility in ways that no other technology can match. Page Motorola Programmable Arrays (MPA) . . . . . . . . . . . . 3.1-1 Selection by Function Logic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1-8 Device Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1-36 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1-46 Case Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1-50 Packaging Information . . . . . . . . . . . . . . . . . . . . . . . . . 3.1-83 Surface Mount . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1-83 Pin Conversion Tables . . . . . . . . . . . . . . . . . . . . . . . 3.1-83 Tape and Reel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1-84
Motorola Master Selection Guide
3.0-1
Logic: Standard, Special and Programmable
INTRODUCTION TO MOTOROLA PROGRAMMABLE ARRAYS AND THE MPA DESIGN SYSTEM
Field programmable logic and in particular, field programmable arrays, have become the solution of choice for logic design implementation in applications where time to market is a critical product development factor. In addition, reconfigurable arrays have been used to enhance Customer product flexibility in ways that no other technology can match. Programmable logic not only vastly reduces the time necessary to implement a static design, but significant product feature benefits can be realized when hardware can be dynamically altered as easily as software. The reconfigurable Motorola Programmable Array (MPA) and MPA design system maximize application flexibility and minimize time to market by delivering a gate level, push button, programmable logic solution.
Design Capture
Logic system designers have two basic options when selecting a method for capturing their designs. For smaller or very regular designs, schematic capture continues to be a popular design entry vehicle. With the increasing size and complexity of today's designs coupled with decreasing design cycle time requirements, many designers are turning to Hardware Description Languages (HDLs). The MPA family was designed from the outset to be well suited to both methodologies. The output of logic synthesis compilers maps effortlessly and efficiently onto the MPA architecture. Unlike other FPGA offerings, the MPA poses no significant architectural limitations for which the designer might otherwise have to adjust his schematic design techniques for. Push Button Design Implementation The MPA design system minimizes training investment and automatically generates design implementations which meet timing constraints. The gate level logic and abundant hierarchical routing resources of the MPA device present a rich implementation media for design implementation. MPA design tools understand and optimally utilize the MPA device resources so there are no elaborate rules to learn or design modifications required to begin design capture. Staying focused on end product design rather than implementation tools or device architecture gets the design done faster and, unlike other programmable solutions, without programmable logic device specificity to impede future design migration efforts. The combination of automatic tools and gate level
architecture is ideal for traditional schematic driven or high level language based design capture methods. In fact, logic synthesis tools were originally designed for and produce the most efficient results for targeting gate level devices. A design is analyzed, optimized, transformed into MPA cells, partitioned, placed and routed based on timing constraints for all paths in the design - automatically. A netlist from one of the popular design capture systems or an existing XNF or LPM netlist is imported into the MPA design system. The logic is mapped to a series of MPA cells and the entire resulting netlist is optimized and checked. Based on a simple clock specification, the MPA design system generates timing constraints for all paths in the design. During automatic partitioning, placement and routing path slack time is constantly redistributed insuring only the resources required to meet timing requirements are consumed. Because MPA tools implement the design according to constraints, tool induced design iterations are virtually eliminated. Completed layouts can be transformed into device configurations, as well as annotated simulation netlists. A layout browser is also available. The MPA design system also includes complete on-line, hypermedia, help covers the device, the design system and the integration kits. Integration kits for Viewlogic, Exemplar, VHDL (1076 and SDF), Verilog (OVI and SDF) and OrCAD are included (contact your vendor for additional kits).All these features add up to a powerful yet extremely easy to use design implementation engine for the MPA product family. Design Importation Designs can be captured using schematics, a high level language, or a combination of these entry methods using commercially available design capture and logic synthesis software and the appropriate interface kit. Alternatively, existing designs can be retargeted from other programmable logic devices to the MPA device using commercial logic synthesis tools or the powerful retargetting capabilities provided with MPA design system. Design importation begins with a netlist and an optional clock specification file. The clock specification file provides a mechanism for the user or design capture tools to document system level timing requirements. In addition, a rich set of attributes can be attached to specific components or nets within the design to specify timing and design pinout constraints.
Motorola Master Selection Guide
3.1-1
Logic: Standard, Special and Programmable
A retargetting rules file is read and the input netlist is transformed into a series of MPA cells and associated interconnections. Rules files provide a mechanism to perform attribute mapping, cell mapping and macro expansion. By creating custom rule files, the user can extend the importation process from arbitrary sources. The MPA design system comes with rules for it's native library/EDIF. The resulting netlist is optimized to clip unused logic and remove redundant logic. For example: each MPA cell has programmable input inversion capability. All Inverters or non-inverting buffers can be removed from the netlist and replaced with signal sense information attached to each input. A series of design rule checks are performed to insure design integrity before the layout process begins. Constraint Generation Timing constraints, the optimized MPA netlist and static timing analysis is used to generate path slack constraints for all paths in the design. Each unique signal pathway between a register output and a register input throughout the design are enumerated. The total logic and estimated or real wire delays along the path are summed. The time between the active upstream register clock edge and the next active downstream clock edge minus the downstream register setup time is subtracted from the total path delay. This difference is called path slack. If any path in the design has a negative slack value, the implementation will not function at the required clock rate(s). Path constraints are utilized throughout the layout process to insure that a design implementation which meets timing constraints is automatically generated. If no clock or timing specifications are provided, the MPA design system uses the fastest possible clock based on very small net delay estimates to generate the path constraints. This usually results in the best possible implementation, but may take longer than the time required to generate a satisfactory rather than best possible result. Contrast this to other programmable logic design tools which only provide manual net constraint annotation or net criticality assignment. In these cases significant effort is necessary to generate constraints and many costly iterations are required to tune these constraints for a given design. If any changes are made to the design, another costly round of iterations is required. Autolayout The autolayout process makes use of the hierarchical organization of the MPA device to minimize run time and deliver implementations that meet timing requirements. Designs which have diverse timing requirements are ideally implemented because path slack estimates are refined throughout the autolayout process insuring only the resources required to meet timing requirements are consumed. The process begins by flattening the design and partitioning it into small component groups of approximately
the same size called clusters. A cluster boundary delay estimation is applied to pull the most tightly constrained paths into a minimum number of clusters. The clusters are then assigned to zones talking into account zonal boundary delay cost and relative zone placement delay costs. Other costs like total number of port connections per zone and are also considered. As assignment proceeds, cluster and zone boundary delay costs are added to each path and slack is recomputed. Next global placement and routing is done. Global routes begin and end on either I/O cells or port cells. Intrazone placement and routing is deferred to a later phase. During global routing all the port cell and I/O cell locations are fixed and the connections between them established. High fanout nets are constructed in a highly regular manner to insure efficient resource utilization. As in partitioning, slack estimates are refined throughout global routing. Finally the intrazonal placement and routing is done. Cells assigned to a particular zone are placed and routed to other zone cells or zone port cells. Port cells and core cells are constructed to allow port swapping. Core cells can be routed through if necessary. Allowing core cells to act as routing cells allows dynamic adjustment of routing resources within the zone. Dynamic resource adjustment is a powerful design specific adaptation mechanism. This process produces a layout from which device configurations, delay back annotations, and chipviews can be generated. Incremental Design Support When specification changes necessitate design iterations, simply push the button again. Constraints are automatically recalculated and autolayout only reworks those portions of the design which have changed. Full incremental design support means simple design changes to facilitate design verification can be made quickly and easily. Delay Back Annotation Designs can be verified through numerous methods. One particularly useful method is the annotation of device and implementation specific delays back into the original simulation environment to improve system or device level simulation accuracy. A MPA device layout can be transformed into an appropriately formatted delay annotation file or annotated netlist quickly and easily. The annotated delay information represents the worst case delays for a given device speed grade. Chipview While the MPA design system provides a rich set of reports describing the implementation of a design, a graphical view of the implementation can be indispensable for reviewing overall layout quality. Chipview provides a graphical view of a completed layout. Chipview can be useful during initial design iterations to visually verify I/O pin placements before commencing PCB layout, for example.
Logic: Standard, Special and Programmable
3.1-2
Motorola Master Selection Guide
Configuration A layout can be transformed into a device configuration which, when loaded into the appropriate MPA device, produces a physical design realization. Many formatting options are available. The MPA download pod can be used to emulate a serial PROM. Using the pod, device configuration files can be downloaded to a device directly from the PC or workstation development environment. Integration Kits The MPA design system can be used with a large number of commercial electronic design automation software. For each supported vendor, an integration kit is provided which facilitates MPA design within that vendors' environment. Many of these kits are available from Motorola and included
at no charge on the MPA design system CDROM. Other kits can be acquired directly from the vendor. Refer to the MPA Design System Product List for more information. Low Cost, Easy Access MPA Design systems are easy to use, competitively priced and widely available. Copies of MPA design system software supporting up to 8000 gates can be downloaded from the World Wide Web (WWW) at URL: http://sps.motorola.com/fpga Complete kits including download pod, evaluation board, MPA device, CDROM and documentation can be ordered from your local authorized Motorola distributor or Motorola sales representative.
Motorola Master Selection Guide
3.1-3
Logic: Standard, Special and Programmable
MOTOROLA
Motorola Programmable Array Design System
SEMICONDUCTOR TECHNICAL DATA
MPA Family Overview
DESIGN SYSTEM
The Motorola Programmable Array (MPA) design system is a bridge between a design capture environment and Motorola field programmable arrays. The MPA design system automatically transforms designs into device configurations to realize a design, when loaded into an MPA device. A design is automatically analyzed, optimized, transformed into MPA cells, partitioned, placed and routed based on timing constraints for every path in the design. MPA design tools understand and optimally utilize the MPA device architecture; this eliminates the need to learn a new set of rules and makes these tools ideally suited for use with logic synthesis. Full incremental design support reduces design implementation time and powerful library retargeting capabilities allow you to reuse designs which may have been implemented on less capable devices. The MPA design system operates on existing hardware platforms and supports design capture and simulation tools from more than 10 vendors. All these features plus on-line, hypermedia, help make the MPA design system a powerful, yet extremely easy to use, design implementation engine. Features * * * * * * * * Push Button Implementation Optimal Use of MPA Device Resources Optimal Results with Gate Level Design Input Library of Common MSI Functions Design Flow Manager Design Retargeter Timing Driven with Integrated Static Timing Analysis Layout Delay extraction for post layout simulation * Layout viewer * Incremental design support * On-line, hypermedia, documentation * Supports all popular design capture and simulation tools * Lowest cost FPGA development systems. * Instant access; Downloading via the internet (WWW, ftp). * Supports multiple speed grades
Design Importation * Read Appropriate Rules File * Retarget to MPA Primitives * Macro Expansion * Design Optimization * Design Rule Checks Constraint Generation * Read User Constraints * Path Enumeration * Path Constraint Generation
Chipview * Read Stored Layout * Construct Graphical
Representation
Timing Driven Autolayout * Partition Design Into Clusters * Assign Clusters to Zones * Global Place & Route * Zonal Place & Route * Continuous Slack
Redistribution
Delay Annotation * Read Stored Layout * Construct Annotated
Netlist
Configuration * Read Stored Layout * Construct Bitstream MPA Device
Logic: Standard, Special and Programmable
3.1-4
Motorola Master Selection Guide
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MPA Family Overview
MPA1000 Programmable Arrays
Motorola Programmable Array (MPA) products are a high density, high performance, low cost, solution for your reconfigurable logic needs. When used with our automatic high performance design tools, MPA delivers custom logic solutions in minutes rather than weeks. And the low cost keeps those solutions competitive throughout the product lifecycle. The MPA architecture has solved the historical problems associated with fine grain devices without sacrificing re-programmability, reliability, or cost. MPA1000 devices are reprogrammable SRAM based products manufactured on a standard 0.43 Leff CMOS process with logic capacities from 3,500 to more than 22,000 equivalent FPGA gates. MPA Logic resources hold a single gate or storage element providing a highly efficient, adaptable, design implementation medium. Gate level logic resources, abundant hierarchical interconnection resources and automatic, timing driven, tools work together to quickly provide design implementations that meet timing constraints without sacrificing device utilization. Staying focused on end product design rather than implementation tools or device architecture gets the design done faster and, unlike other programmable solutions, without programmable logic device specificity to impede future design migration efforts. The combination of automatic tools and gate level architecture is ideal for traditional schematic driven or high level language based design methodologies. In fact, logic synthesis tools were originally designed for and produce the most efficient results when targeting gate level devices. High MPA1000 register count and controlled clock skew is ideal for designs employing pipelining techniques such as communications. The unique set of MPA1000 I/O programming options make these devices suitable for industrial and computer interfacing circuits.
MPA1016 MPA1036 MPA1064 MPA1100
PROGRAMMABLE ARRAY 3,500 to 22,000 GATES
* * * * * * * *
Multiple I/O from 80-200 I/O Pins Programmable 3V/5V I/O at Any Site Multiple Packaging Options Fine Grain Structure Is Optimized for Logic Synthesis Programmable Output Drive, 4/6mA @ 5.0V and 3.3V High Register Count, with 560-2,900 Flip-Flops IEEE 1149.1 JTAG Boundary Scan Eight Low-Skew (<1ns) Clocks
MPA1000 Family Members
FPGA Gates* 3500 8000 Part No. MPA1016FN MPA1016DD MPA1036FN MPA1036DD MPA1036DH MPA1036HI MPA1064DH MPA1064DK MPA1064KE MPA1064BG MPA1100DK MPA1100HV MPA1100BG Logic Cells 1600 3600 Internal Flip-Flops 400 900 I/O Cell Flip-Flops 122 160 122 160 240 240 240 320 320 320 320 400 400 Avail I/O Pins 61 80 61 80 120 120 120 160 160 160 160 200 200 Packages 84 PLCC 128 PQFP 84 PLCC 128 PQFP 160 PQFP 181 PGA 160 PQFP 208 PQFP 224 PGA 256 PBGA 208 PQFP 299 PGA 256 PBGA Availability NOW NOW NOW NOW NOW NOW NOW NOW NOW 3Q97 NOW NOW 3Q97
14200
6400
1600
22000
10000
2500
* Equivalent to Industry Standards, as supplied by most manufacturers.
Motorola Master Selection Guide
3.1-5
Logic: Standard, Special and Programmable
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MPA Family Overview
MPA17000 Serial EPROMs
The MPA17128, MPA1765 serial OTP EPROMs provide a compact, low pin count, non-volatile configuration store for MPA1000 devices. MPA17000 devices can be cascaded for increased memory capacity when needed. They are available in the standard 8-pin plastic DIP (N suffix), 8-pin SOIC (D suffix) and 20-pin PLCC (FN suffix) packages.
MPA17128 MPA1765
* Configuration EPROM for MPA1000 Devices
* * * * * * * * * * Voltage Range -- 4.5 to 6.0V Maximum Read Current of 10mA Standby Current of 10A, Typical Industry Standard Synchronous Serial Interface Full Static Operation 10MHz Maximum Clock Rate at 5.0V Programmable Polarity on Hardware Reset Programs With Industry Standard Programmers Electrostatic Discharge Protection > 2000 Volts 8-Pin PDIP and SOIC; 20-Pin PLCC Packages
128K, 64K SERIAL EPROM
8 1
* Commercial (0 to +70C) and Industrial (-40 to +85C)
P SUFFIX PLASTIC PACKAGE CASE 626-05
8-Lead Pinouts (Top View)
8
DATA 1 CLK 2 RESET/OE 3 CE 4
8 VCC 7 Vpp 6 CEO 5 Vss
1
D SUFFIX PLASTIC SOIC PACKAGE CASE 751-05
19 3 4
8
20-Lead Pinout (Top View)
NC 18 NC VCC NC DATA NC 19 20 1 2 3 4 5 6 7 8 CE Vpp 17 NC 16 NC CEO 15 14 13 12 11 10 9 NC NC NC Vss NC
FN SUFFIX PLCC PACKAGE CASE 775-02
PIN NAMES
Pins DATA CLK RESET/OE CE VSS CEO VPP VCC NC Function Data I/O Clock Reset Input and Output Enable Chip Enable Input Ground Chip Enable Output Programming Voltage Supply +4.5 to 6.0V Power Supply Not Connected
CLK NC RESET/ NC OE
Logic: Standard, Special and Programmable
3.1-6
Motorola Master Selection Guide
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MPA Family Overview
Advance Information MPA17000 Serial EEPROM
The MPA17C256 is an easy to use and cost effective serial configuration memory ideally suited for use with today's popular SRAM based FPGAs. The MPA17C256 is available in 8-pin PDIP and 20-pin SOIC and PLCC packages, adhering to industry standard pinouts. The device interfaces downstream FPGA(s) with a very simple enable, clock and data interface. The MPA17C256 is reprogrammable with no need for a higher programming "super voltage"; it may even be reprogrammed on board. The MPA17C256 also has user programmable RESET/OE polarity.
MPA17C256
MPA17C256
* EE Programmable 262,144 x 1 bit Serial Memories Designed to Store
Configuration Programs for FPGAs * Simple Interface to SRAM FPGAs * Cascadable to Support Additional Configurations or Future Higher Density FPGAs * Low Power CMOS EEPROM Process * Programmable Reset Polarity * Available in Space Efficient 8-Pin PDIP, 20-Pin SOIC and 20-Pin PLCC Packages
P SUFFIX 8-LEAD PLASTIC PACKAGE CASE 626-05
DW SUFFIX 20-LEAD PLASTIC SOIC WIDE PACKAGE CASE 751D-04
* In-System Programmable via 2-Wire Bus
FN SUFFIX 20-LEAD PLCC PACKAGE CASE 775-02
Controlling the MPA17C256 Serial EEPROM Most connections between the FPGA device and the Serial EEPROM are simple and self-explanatory:
PIN NAMES
* The DATA output of the MPA17C256 drives DIN of the FPGA devices
* The master FPGA DCLK output drives the CLK input of the MPA17C256 * The CEO output of the first MPA17C256 drives the CE input of the next MPA17C256 in a cascade chain of EEPROMs. * SER_EN must be connected to VCC * CE enables the chip and is required to enable the DATA output pin
Pins DATA CLK RESET/OE CE VSS CEO SER_EN VCC NC
Function Data I/O Clock Reset Input and Output Enable Chip Enable Input Ground Chip Enable Output Programming Enable +4.5 to 6.0V Power Supply Not Connected
* RESET/OE is chip reset and is part of the DATA output enable structure
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Motorola Master Selection Guide
3.1-7
Logic: Standard, Special and Programmable
Selection by Function
In order to better serve our customers, we have made some modifications to the Selection by Function portion of the Logic Selector Guide. For easy selection of Logic's newer, more complex functions, as well as standard family functions, refer to the subject index below. Within the Selection by Function tables on the next 27 pages, you will find functions sorted by these broad subjects, and then broken down alphabetically into more precise functions.
Logic Functions
AMPLIFIER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1-9 ARITHMETIC OPERATORS . . . . . . . . . . . . . . . . . . 3.1-9 BOUNCE ELIMINATOR . . . . . . . . . . . . . . . . . . . . . . 3.1-9 BUFFERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1-9 BUFFERS, 3-STATE . . . . . . . . . . . . . . . . . . . . . . . . . 3.1-9 BUS INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1-10 CBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1-12 CLOCK DISTRIBUTION CHIPS . . . . . . . . . . . . . . 3.1-12 CLOCK DRIVERS . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1-12 COAX CABLE DRIVERS . . . . . . . . . . . . . . . . . . . . 3.1-13 COMPARATORS . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1-14 CONVERTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1-14 COUNTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1-14 DECODER/DEMULTIPLEXERS . . . . . . . . . . . . . . 3.1-16 DETECTORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1-17 DISPLAY DECODE DRIVERS . . . . . . . . . . . . . . . . 3.1-17 DIVIDERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1-17 DRIVER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1-17 EDACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1-17 ENCODERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1-17 ENCODER/DECODERS . . . . . . . . . . . . . . . . . . . . . 3.1-18 EXPANDERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1-18 FIELD PROGRAMMABLE GATE ARRAYS . . . . . 3.1-18 FLIP-FLOPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1-18 GATES, AND/NAND . . . . . . . . . . . . . . . . . . . . . . . . 3.1-21 GATES, COMPLEX . . . . . . . . . . . . . . . . . . . . . . . . . 3.1-22 GATES, EXCLUSIVE OR/EXCLUSIVE NOR . . . 3.1-23 GATES, NOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1-24 GATES, OR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . INDUSTRIAL CONTROL UNIT . . . . . . . . . . . . . . . INVERTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . INVERTER/BUFFERS, 2-STATE . . . . . . . . . . . . . LATCHES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MEMORY SUPPORT . . . . . . . . . . . . . . . . . . . . . . . MISCELLANEOUS . . . . . . . . . . . . . . . . . . . . . . . . . MULTIPLEXER/DATA SELECTORS . . . . . . . . . . . MULTIVIBRATORS . . . . . . . . . . . . . . . . . . . . . . . . . OSCILLATORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OSCILLATOR/TIMERS . . . . . . . . . . . . . . . . . . . . . . PARITY CHECKERS . . . . . . . . . . . . . . . . . . . . . . . . PHASE-LOCKED LOOP . . . . . . . . . . . . . . . . . . . . PRESCALERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PROGRAMMABLE DELAY CHIPS . . . . . . . . . . . . RAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RECEIVERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REGISTER FILES . . . . . . . . . . . . . . . . . . . . . . . . . . SCHMITT TRIGGERS . . . . . . . . . . . . . . . . . . . . . . . SCSI BUS TERMINATORS . . . . . . . . . . . . . . . . . . SERIAL EPROMs . . . . . . . . . . . . . . . . . . . . . . . . . . SHIFT REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . SYNTHESIZERS . . . . . . . . . . . . . . . . . . . . . . . . . . . TRANSCEIVERS . . . . . . . . . . . . . . . . . . . . . . . . . . . TRANSLATORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1-24 3.1-25 3.1-25 3.1-25 3.1-26 3.1-27 3.1-27 3.1-27 3.1-29 3.1-29 3.1-30 3.1-30 3.1-30 3.1-30 3.1-31 3.1-31 3.1-31 3.1-32 3.1-32 3.1-32 3.1-32 3.1-32 3.1-32 3.1-34 3.1-34 3.1-34 3.1-35
Logic: Standard, Special and Programmable
3.1-8
Motorola Master Selection Guide
Selection by Function
Description
AMPLIFIER
Tech.
Device(s)
Pins
DIP
SM
Fiber Optic Post Amplifier
ARITHMETIC OPERATORS
ECL TTL TTL TTL
MC10SX1125 MC74F181 MC74F381 MC74F382 MC10H181
- - - - -
16 24 20 20 24 N N N P,L, PW, LW P,L N N,J N,J P,L P P N P,L P,L P,L P,L L P,L
D DW DW DW FN
4-Bit Arithmetic Logic Unit
4-Bit Arithmetic Logic Unit/Function Generator
ECL
ECL 4-Bit Binary Full Adder With Fast Carry TTL TTL TTL 4-Bit Full Adder 9's Complementer BCD Rate Multiplier Carry Lookahead Generator Dual 2-Bit Adder/Subtractor Look Ahead Carry Block NBCD Adder Triple Serial Adder (Negative Logic)
BOUNCE ELIMINATOR
MC10181 MC74F283 SN54LS83A SN54LS283 MC14008B MC14561B MC14527B MC74F182 MC10H180 MC10180 MC10H179 MC14560B MC14038B MC14490 MC100LVEL11 MC100LVE310 MC100LVEL13 MC832 MC100LVE210
- - SN74LS83A SN74LS283 - - - - - - - - - - - MC100E310 MC100EL13 - MC100E210
24 16 14 16 16 14 16 16 16 16 16 16 16 16 8 28 20 14 28
D D D D D DW D FN FN D
CMOS CMOS CMOS TTL ECL ECL ECL CMOS CMOS CMOS ECL ECL ECL DTL ECL
Hex Contact Bounce Eliminator
BUFFERS
DW D FN DW
1:2 Differential Fanout Buffer 2:8 Differential Fanout Buffer Dual 1:3 Fanout Buffer Expandable Buffer Low Voltage Dual 1:4, 1:5 Differential Fanout Buffer, ECL/PECL Compatible
BUFFERS, 3-STATE
P,L FN
Low-Voltage CMOS 16-Bit Buffer, 3-State, Inverting With 5V Tolerant Inputs and Outputs Low-Voltage CMOS 16-Bit Buffer, 3-State, Non-Inverting With 5V Tolerant Inputs and Outputs Low-Voltage CMOS Octal Buffer, 3-State, Non-Inverting With 5V Tolerant Inputs and Outputs Low-Voltage CMOS Octal Buffer, 3-State, Inverting With 5V Tolerant Inputs and Outputs Low-Voltage CMOS Octal Buffer Flow Through Pinout, 3-State, Non-Inverting With 5V Tolerant Inputs and Outputs Low-Voltage CMOS Octal Buffer Flow Through Pinout, 3-State, Inverting With 5V Tolerant Inputs and Outputs Low-Voltage CMOS Quad Buffer, 3-State, Inverting With 5V Tolerant Inputs and Outputs Low-Voltage Quiet CMOS Octal Buffer Low-Voltage Quiet CMOS Octal Buffer, 3-State, Non-Inverting
CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS
MC74LCX16240A MC74LCX16244
- - - - - - - - -
20 20 20 20 20 20 20 20 20
DW,M, DT DW,M, DT DW,M, DT DW,M, DT DW,M, DT DW,M, DT DW,M, DT D,M, SD,DT DW,M, SD,DT
MC74LCX244 MC74LCX240 MC74LCX541 MC74LCX540 MC74LCX125 MC74LVQ541 MC74LVQ244
Motorola Master Selection Guide
3.1-9
Logic: Standard, Special and Programmable
Selection by Function
Description
BUFFERS, 3-STATE
Tech. CMOS CMOS
Device(s) MC74LVQ240 MC74LVQ125 - -
Pins 20 14
DIP
SM DW,M, SD,DT D,M, SD,DT
Low-Voltage Quiet CMOS Octal Buffer, 3-State, Inverting Low-Voltage Quiet CMOS Quad Buffer, 3-State, Non-Inverting
BUS INTERFACE
10-Bit Buffer/Line Driver (Inverting), With 3-State Outputs 10-Bit Buffer/Line Driver (Non-Inverting), With 3-State Outputs 3-Bit Registered Bus Transceiver, 25 Cutoff Outputs 3-Bit Scannable Registered Bus Transceiver 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer 9-Bit Bus Interface, NINV, 3 State Outputs Dual Bus Driver/Receiver With 4-to-1 Output Multiplexer (25) Hex 3-State Inverting Buffer With Common Enables Hex 3-State Inverting Buffer With Separate 2-Bit and 4-Bit Sections Hex 3-State Non-Inverting Buffer With Common Enables Hex 3-State Non-Inverting Buffer With Separate 2-Bit and 4-Bit Sections Hex Buffer 4/2-Bit/Inverting With 3-State Outputs Hex Buffer 4/2-Bit/Non-Inverting With 3-State Outputs Hex Buffer Driver, 4+2-Bit, Inverting, With 3-State Outputs Hex Buffer Gated Enable Inverting With 3-State Outputs Hex Buffer Gated Enable Non-Inverting With 3-State Outputs Hex Buffer/Driver Gated Enable Inverting, With 3-State Outputs Hex Buffer/Driver Gated Enable Non-Inverting, With 3-State Outputs Hex Buffer/Driver, 4+2-Bit, Non-Inverting, With 3-State Outputs Hex With 3-State Outputs Buffer (Non-Inverting) Octal 3-State Non-Inverting Bus Transceiver With LSTTL Compatible Inputs Octal Bidirectional Transceiver With 3-State Inputs/Outputs Octal Bidirectional Transceiver With 3-State Outputs
TTL TTL ECL ECL CMOS CMOS TTL ECL CMOS CMOS CMOS CMOS TTL TTL TTL TTL TTL TTL TTL TTL CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS TTL
MC74F828 MC74F827 MC10E336 MC10E337 MC68150*33 MC68150*40 MC74F823 MC10H332 MC54HC366 MC74HC368 MC54HC365 MC54HC367 SN54LS368A SN54LS367A MC74F368 SN54LS366A SN54LS365A MC74F366 MC74F365 MC74F367 MC14503B MC54HCT245A MC74AC245 MC74ACT245 MC74AC620 MC74ACT620 MC74AC623 MC74ACT623 MC74AC640 MC74ACT640 MC74AC643 MC74ACT643 MC74F245 MC74F657A MC74F657B MC74F1245 SN54LS795 SN54LS796 SN54LS797 SN54LS798
- - MC100E336 MC100E337 - - - - MC74HC366 - MC74HC365 MC74HC367 SN74LS368A SN74LS367A - SN74LS366A SN74LS365A - - - - MC74HCT245A - - - - - - - - - - - - - - SN74LS795 SN74LS796 SN74LS797 SN74LS798
24 24 28 28 68 68 24 20 16 16 16 16 16 16 16 16 16 16 16 16 16 20 20 20 20 20 20 20 20 20 20 20 20 24 24 20 20 20 20 20
N N
DW DW FN FN FN FN
N P,L N,J N N,J N,J N,J N,J N N,J N,J N N N P,L N,J N N N N N N N N N N N N N N N,J N,J N,J N,J
DW FN
DT
D D D D D D D D D DW, SD,DT DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW
Octal Bidirectional Transceiver With 8-Bit Parity Generator y Checker With 3 State O tp ts Checker, 3-State Outputs Octal Bidirectional Transceiver, With 3-State Inputs/Outputs Octal Buffer With 3-State Outputs
TTL TTL TTL
(81LS95) TTL (81LS96) TTL (81LS97) TTL (81LS98) TTL
Logic: Standard, Special and Programmable
3.1-10
Motorola Master Selection Guide
Selection by Function
Description
BUS INTERFACE
Tech. TTL TTL TTL TTL TTL TTL TTL TTL CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS SN54LS244 MC74F240 MC74F241 MC74F244 SN54LS240 SN54LS241 SN54LS540 SN54LS541 MC74AC241 MC74AC244
Device(s) SN74LS244 - - - SN74LS240 SN74LS241 SN74LS540 SN74LS541 - - - - - - - - - - SN74LS245 SN74LS623 - SN74LS640 - - SN74LS645 - - - - - - - - MC74HC241A MC74HCT241A MC74HCT244A MC74HC240A MC74HC540A - MC74HC640A MC74HC541A - -
Pins 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 24 24 24 24 24 24 24 24 20 20 20 20 20 20 20 20 20 20
DIP N,J N N N N,J N,J N,J N,J N N N N N N N N N N N,J N,J N N,J N N N,J N N N N N N N N N,J N,J N,J N,J N,J N N,J N,J
SM DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW, SD,DT DW, DT DW DW, SD,DT DW DW DW, DT,M
Octal Buffer/Line Driver With 3-State Outputs
MC74ACT244 MC74AC540 MC74ACT540 MC74AC541 MC74ACT541 MC74AC240 MC74ACT240 MC74ACT241 SN54LS245 SN54LS623 MC74F623 SN54LS640 MC74F620 MC74F640 SN54LS645 MC74AC652 MC74ACT652 MC74F544 MC74AC646 MC74ACT646 MC74AC648 MC74ACT648 MC74F646 MC54HC241A MC54HCT241A MC54HCT244A MC54HC240A MC54HC540A MC74HCT240A MC54HC640A MC54HC541A MC74VHC541 MC74HCT541A
Octal Bus Transceiver Octal Bus Transceiver, With 3-State Outputs Octal Bus Transceiver/Inverting With 3-State Outputs
TTL TTL TTL TTL TTL TTL
Octal Bus Transceiver/Non-Inverting With 3-State Outputs Octal Bus Transceiver/Register With 3-State Outputs Non-Inverting Octal Registered Transceiver Inverting, With 3-State Outputs Octal Transceiver/Register With 3-State Outputs Non-Inverting Octal Transceiver/Register With 3-State Outputs Inverting Octal Transceiver/Register, With 3-State Outputs Octal With 3-State Non-Inverting Buffer/Line Driver/Line Receiver Octal With 3-State Non-Inverting Buffer/Line Driver/Line Receiver g With LSTTL Compatible Inputs Octal With 3-State Outputs Inverting Buffer/Line Driver/Line Receiver Octal With 3-State Outputs Inverting Buffer/Line Driver/Line Receiver With LSTTL Compatible Inputs Octal With 3-State Outputs Inverting Bus Transceiver Octal With 3-State Outputs Non-Inverting Buffer/Line Driver/Line Receiver
TTL CMOS CMOS TTL CMOS CMOS CMOS CMOS TTL CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS
Octal With 3-State Outputs Non-Inverting Buffer/Line Driver/Line Receiver With LSTTL Compatible Inputs
CMOS
N
DW
Motorola Master Selection Guide
3.1-11
Logic: Standard, Special and Programmable
Selection by Function
Description
BUS INTERFACE
Tech. CMOS CMOS
Device(s) MC54HC244A MC74VHC244 MC54HC245A MC74VHC245 MC54HC646 SN54LS125A MC74HC125A MC74VHC125 MC74HC126A MC74AC125 MC74ACT125 MC74AC126 MC74ACT126 MC74F125 MC74F126 SN54LS126A MC10192 MC10H330 MC10H334 SN54LS242 SN54LS243 MC74F242 MC74F243 MC74HC242 MC10H423 MC10H123 MC10123 MC68194 MC10EL15 MC100LVEL14 MC10E211 MPC948 MPC948L MPC947 MC100LVE111 MC10EL11 MPC903 MPC904 MPC905 MC10E111 MC74HC244A - MC74HC245A - MC74HC646 SN74LS125A - - - - - - - - - SN74LS126A - - - SN74LS242 SN74LS243 - - - - - - - MC100EL15 MC100EL14 MC100E211 - - - - MC100EL11 - - - MC100E111
Pins 20 20 20 20 24 14 14 14 14 14 14 14 14 14 14 14 16 24 20 14 14 14 14 14 16 16 16 52 16 20 28 32 32 32 28 8 16 16 16 28
DIP N,J
SM DW, SD,DT DW, DT,M
Octal With 3-State Outputs Non-Inverting Buffer/Line Driver/Line Receiver
Octal With 3-State Outputs Non-Inverting Bus Transceiver
CMOS CMOS
N,J
DW DW DT,M
Octal With 3-State Outputs Non-Inverting Bus Transceiver & D Flip-Flop Quad Buffers With 3-State Outputs Quad 3-State Non-Inverting Buffers
CMOS TTL CMOS CMOS CMOS
N,J N,J N
DW D D,DT D, DT,M
N N N N N N N N,J P,L P,L P,L N,J N,J N N N P,L P,L P,L
D,DT D D D D D D D FN FN FN D D D D FN FN FN *FJ D DW FN FA FA FA FN D D D D FN
Quad Buffer With 3-State Outputs
CMOS CMOS CMOS CMOS TTL TTL TTL
Quad Bus Driver Quad Bus Driver/Receiver With 2-to-1 Output Multiplexer (25) Quad Bus Driver/Receiver With Transmit & Receiver Latches (25) Quad Bus Transceiver/Inverting With 3-State Outputs Quad Bus Transceiver/Non-Inverting With 3-State Outputs Quad Bus Transceivers With 3-State Outputs Quad With 3-State Outputs Inverting Bus Transceiver Triple 3-Input Bus Driver With Enable (25) Triple 4-3-3 Input Bus Driver (25)
CBM
ECL ECL ECL TTL TTL TTL TTL CMOS ECL ECL ECL
CBM - Carrier Band Modem
CLOCK DISTRIBUTION CHIPS
SXLG ECL ECL ECL SXLG SXLG SXLG ECL ECL CMOS CMOS CMOS
1:4 Clock Distribution Chip 1:5 Clock Distribution Chip 1:6 Differential Clock Distribution Chip Low Voltage 1:12 Clock Distribution Chip Low Voltage 1:9 Clock Distribution Chip Low Voltage 1:9 ECL/PECL Clock Distribution Chip
CLOCK DRIVERS
1:2 Differential Clock Driver 1:6 PCI Clock Generator/Fanout Buffer
1:9 Differential Clock Driver With Low Skew, Enable, Vbb
ECL
Logic: Standard, Special and Programmable
3.1-12
Motorola Master Selection Guide
Selection by Function
Description
CLOCK DRIVERS
Tech. ECL ECL CMOS CMOS CMOS ECL ECL ECL MC10E411 MC10H645 MPC974 MC88920 MC88921 MC10H640 MC10H642 MC10H644 MC74F1803 MC74F803 MC88PL117 MPC980 MC10H643 MC12429 MC12430 MC12439 MC88913 MC88914 MC88LV926
Device(s) - - - - - MC100H640 MC100H642 MC100H644 - - - - MC100H643 - - - - - - - - - - - - - - - - - - - - MPC931 MPC951 - - MPC973 MPC991 - MC100H646 MC100H641 MC100EL38 MC100EL39 MC100EL34 - -
Pins 28 28 52 20 20 28 28 20 14 14 52 52 28 28 28 28 14 14 20 28 28 20 20 28 28 28 28 28 32 52 52 28 32 32 32 32 52 52 52 32 28 28 20 20 16 16 16
DIP
SM FN FN FA DW DW FN FN FN
1:9 Differential ECL/PECL RAMBus Clock Buffer 1:9 TTL/TTL Clock Distribution Chip 3.3/5.0V Fully Integrated PLL Clock Driver 50 MHz Low Skew CMOS PLL Clock Driver With P Power Down 66 MHz Low Skew CMOS PLL Clock Driver With P Power-Down/Power-Up Feature 68030/040 PECL/TTL Clock Driver
Clock Driver Quad D-Type Flip-Flop w/ Matched Propagation Delays CMOS PLL Clock Driver Programmable Frequency, Low Skew, High Fan-Out Dual 3.3V PLL Clock Generator Dual Supply ECL/TTL 1:8 Clock Driver High Frequency PLL Clock Generator
TTL TTL CMOS CMOS ECL ECL ECL ECL
N N
D D FN FA FN FN FN FN
Low Skew CMOS Clock Driver Low Skew CMOS Clock Driver With Reset Low Skew CMOS PLL 68060 Clock Driver Low Skew CMOS PLL Clock Driver Low Skew CMOS PLL Clock Driver With Processor Reset Low Skew CMOS PLL Clock Driver 160 MHz Version
CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS 133 MHz Version CMOS 100 MHz Version CMOS 70 MHz Version CMOS 55 MHz Version CMOS
N N
D D DW FN FN DW DW FN FN FN FN FN FA FA FA FN FA FA FA FA FA FA FA FA FN FN DW DW D D D
MC88915*55 MC88915*70 MC88916*70 MC88916*80 MC88915T*160 MC88915T*133 MC88915T*100 MC88915T*70 MC88915T*55 MPC946 MC100LVE222 MPC949 MPC911 MPC992 MPC930 MPC950 MPC956 MPC970 MPC972 MPC990 MPC952 MC10H646 MC10H641 MC100LVEL38 MC100LVEL39 MC10EL34 MC10SX1189 MC10SX1130
Low Voltage 1:10 CMOS Clock Driver Low Voltage 1:15 Differential /1/2 ECL/PECL Clock Driver Low Voltage 1:15 PECL to CMOS Clock Driver Low Voltage 1:9 Differential ECL/HSTL to HSTL Clock Driver Low Voltage PECL PLL Clock Driver Low Voltage PLL Clock Driver
CMOS ECL CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS
Low Voltage Wide Fanout PLL Clock Driver PECL/TTL to TTL 1: 8 Clock Distribution Chip Single Supply PECL/TTL 1:9 Clock Distribution Chip /2, /4/6 Clock Generation Chip (3.3V) /2/4, /4/6 Clock Generation Chip /2,4,8 Differential Clock Driver
COAX CABLE DRIVERS
CMOS ECL ECL ECL ECL ECL SDX SDX
Fibre Channel Coaxial Cable Driver and Loop Resiliency Circuit 300 MBit/s LED Driver for FDDI and Fibre Channel
Motorola Master Selection Guide
3.1-13
Logic: Standard, Special and Programmable
Selection by Function
Description
COMPARATORS
Tech. TTL CMOS TTL CMOS MC74F85 MC74HC85 SN54LS85 MC14585B MC10H166 MC10166
Device(s) - - SN74LS85 - - - MC74HC688 - - SN74LS682 SN74LS684 SN74LS688 MC100E166 - - MC100E446 MC100E445 - - - MC74HC4040A - - - - - MC74HC4060 MC74HC4060A - SN74LS160A SN74LS162A - - SN74LS93 SN74LS293 - - - SN74LS161A SN74LS163A SN74LS569A SN74LS196 SN74LS197 - - - MC100E136 -
Pins 16 16 16 16 16 16 20 20 20 20 20 20 28 16,20 16,20 28 28 16 16 16 16 16 16 16 16 16 16 16 16 16 16 20 20 14 14 16 16 16 16 16 20 14 14 16 16 24 28 14
DIP N N N,J P,L P,L P,L N,J N N N,J N,J N,J L L
SM D DT D D FN FN DW DW DW DW DW FN FN FN FN FN
4-Bit Magnitude Comparator
5-Bit Magnitude Comparator 8-Bit Equality Comparator 8-Bit Identity Comparator 8-Bit Magnitude Comparator
ECL ECL CMOS CMOS TTL TTL TTL TTL
MC54HC688 MC74ACT521 MC74F521 SN54LS682 SN54LS684 SN54LS688 MC10E166 MC10E1651 MC10E1652 MC10E446 MC10E445 MC1650 MC1651 MC14040B MC54HC4040A MC74AC4040 MC14020B MC14060B MC74HC4020A MC74AC4020 MC54HC4060 MC54HC4060A MC14553B SN54LS160A SN54LS162A MC74F569 MC74F568 SN54LS93 SN54LS293 MC10H16 MC14161B MC14163B SN54LS161A SN54LS163A SN54LS569A SN54LS196 SN54LS197 MC74F168 MC74F169 MC14534B MC10E136 MC14024B
9-Bit Magnitude Comparator Dual Analog Comparator With Latch Dual Analog Comparator With Latch (Hi-Perf MC1651)
CONVERTERS
ECL ECL ECL ECL ECL ECL ECL
4-Bit Parallel to Serial Converter 4-Bit Serial to Parallel Converter Dual A/D Converter
COUNTERS
L L P,L N,J N P,L P,L N N N,J N,J P N,J N,J N N N,J N,J P,L P P N,J N,J N,J N,J N,J N N P,L P,L D D,DT D D D D,DT D DT D,DT DW D D DW DW D D FN D D D D DW D D D D DW FN D
12-Bit Binary Counter 12-Stage Binary Ripple Counter 14-Bit Binary Counter 14-Bit Binary Counter and Oscillator 14-Stage Binary Ripple Counter 14-Stage Binary Ripple Counter With Oscillator 3-Digit BCD Counter 4-Bit BCD Decade Counter, Asynchronous Reset 4-Bit Bidirectional Binary Counter, With 3-State Outputs 4-Bit Bidirectional Decade Counter, With 3-State Outputs 4-Bit Binary Counter
CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS TTL TTL TTL TTL TTL TTL ECL
4-Bit Binary Counter, Synchronous Presettable 4-Bit Binary Counter, Synchronous Reset 4-Bit Up/Down Counter With 3-State Outputs 4-Stage Presettable Ripple Counters 4-Stage Synchronous Bidirectional Counter 5 Cascaded BCD Counters 6-Bit Universal Counter, (Lookahead Carry) 7-Stage Ripple Counter
CMOS CMOS TTL TTL TTL TTL TTL TTL TTL CMOS ECL CMOS
Logic: Standard, Special and Programmable
3.1-14
Motorola Master Selection Guide
Selection by Function
Description
COUNTERS
Tech. TTL TTL TTL ECL ECL TTL TTL TTL ECL ECL ECL TTL TTL ECL TTL TTL CMOS CMOS MC74F269 MC74F579 MC74F779 MC10E137 MC10E016 MC74F160A MC74F162A SN54LS168 MC10138 MC10154 MC10178 MC74F161A MC74F163A MC12014 SN54LS90 SN54LS290 MC14017B
Device(s) - - - MC100E137 MC100E016 - - SN74LS168 - - - - - - SN74LS90 SN74LS290 - - SN74LS92 SN74LS393 MC74HC393 MC74HC390 - - SN74LS390 SN74LS490 - SN74LS169 - - - - SN74LS191 SN74LS193 - SN74LS190 SN74LS192 - - MC74HC160 MC74HC161A MC74HCT161A MC74HC162 MC74HC163 MC74HCT163A - -
Pins 24 20 16 28 28 16 16 16 16 16 16 16 16 16 14 14 16 16 14 16 14 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16
DIP N N N
SM DW DW D FN FN
8-Bit Bidirectional Binary Counter 8-Bit Bidirectional Binary Counter, With 3-State Outputs 8-Bit Ripple Counter 8-Bit Synchronous Binary Up Counter BCD Decade Counter, Synchronous Presettable BCD Decade Synchronous Bidirectional Counter Bi-Quinary Counter Binary Counter Binary Counter, Synchronous Presettable, 4-Bit Counter Control Logic Decade Counter
N N N,J P,L P,L P,L N N P,L N,J N,J P,L N N,J N,J N,J N,J P,L P,L N,J N,J P N,J P,L P,L P P,L N,J N,J P N,J N,J P,L P,L N,J N,J N,J N,J N,J N,J P P,L
D D D FN FN D D D D D D D D D D DW DW D D D D D D DW DW D D D D D D D D D D D D D D DW
MC74HC4017 SN54LS92 SN54LS393 MC54HC393 MC54HC390 MC14518B MC14520B SN54LS390 SN54LS490 MC14566B SN54LS169 MC14022B MC14568B MC14522B MC14526B SN54LS191 SN54LS193 MC14510B SN54LS190 SN54LS192 MC14516B MC14029B MC54HC160 MC54HC161A MC54HCT161A MC54HC162 MC54HC163A MC54HCT163A MC14018B MC14569B
Divide By 12 Counter Dual 4-Stage Binary Counter Dual 4-Stage Binary Ripple Counter Dual 4-Stage Binary Ripple Counter W /2, /5 Sections Dual BCD Up Counter Dual Binary Up Counter Dual Decade Counter Industrial Time Base Generator Modulo 16 Binary Synchronous Bidirectional Counter Octal Counter Phase Comparator and Programmable Counter Presettable 4-Bit BCD Down Counter Presettable 4-Bit Binary Down Counter Presettable 4-Bit Binary Up/Down Counter Presettable BCD Up/Down Counter Presettable BCD/Decade Up/Down Counter Presettable Binary Up/Down Counter Presettable Binary/BCD Up/Down Counter Presettable Counter
TTL TTL CMOS CMOS CMOS CMOS TTL TTL CMOS TTL CMOS CMOS CMOS CMOS TTL TTL CMOS TTL TTL CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS
Presettable Divide-by-N Counter Programmable Dual Binary/BCD Counter
CMOS CMOS
Motorola Master Selection Guide
3.1-15
Logic: Standard, Special and Programmable
Selection by Function
Description
COUNTERS
Tech. ECL ECL ECL MC4016 MC4018 MC4316 SN54LS669 MC74AC161
Device(s) - - - SN74LS669 - - - - - - - - - - - - - SN74LS42 SN74LS145 - MC74HC154 - - - - - - MC74HC138A - - SN74LS138 - - SN74LS137 - - MC74HC259 - - - - - - SN74LS155 SN74LS156
Pins 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 20 24 24 20 20 16 16 16 16 16 16 16 16 16 16 24 24 16 16 16 16 16 16 16 16 16
DIP P,L P,L P,L N,J N N N N N N N N P,L P,L P,L N N N,J N,J N N,J N N N N N N N,J
SM
Programmable Modulo-N Counters (N=0-9)
Synchronous 4-Bit Up/Down Counter Synchronous Presettable Binary Counter Synchronous Presettable Binary Counter Synchronous Presettable Binary-Coded-Decimal Decade Counter
TTL CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS
D D D D D D D D D FN FN D D D D DW DW DW DW DW D D D D D,DT, M
MC74ACT161 MC74AC163 MC74ACT163 MC74AC160 MC74ACT160 MC74AC162 MC74ACT162 MC10137 MC10H136 MC10136 MC74AC190 MC74HC42 SN54LS42 SN54LS145 MC74F537 MC54HC154 MC74HC4514 MC74F539 MC74F538 MC74AC138 MC74ACT138 MC74F138 MC54HC138A MC74VHC138 MC74HCT138A SN54LS138 MC74HC137 MC74HC237 SN54LS137 MC14514B MC14515B MC54HC259 MC14028B MC10171 MC10H162 MC10162 MC10H161 MC10161 SN54LS155 SN54LS156
Universal Decade Counter Universal Hexadecimal Counter Up/Down Counter With Preset and Ripple Clock
DECODER/DEMULTIPLEXERS
ECL ECL ECL CMOS CMOS TTL TTL TTL CMOS CMOS TTL TTL CMOS CMOS TTL CMOS CMOS CMOS TTL
1-of-10 Decoder 1-of-10 Decoder/Driver Open-Collector 1-of-10 Decoder, With 3-State Outputs 1-of-16 Decoder/Demultiplexer 1-of-16 Decoder/Demultiplexer With Address Latch 1-of-4 Decoder, With 3-State Outputs 1-of-8 Decoder, With 3-State Outputs 1-of-8 Decoder/Demultiplexer
N N,J N N N,J P,L P,L N,J P,L P,L P,L P,L P,L P,L N,J N,J
D,DT D D D D DW DW D D FN FN FN FN FN D D
1-of-8 Decoder/Demultiplexer With Address Latch 3-Line to 8-Line Decoders/Demultiplexers With Address Latches 4-Bit Transparent Latch/4-to-16 Line Decoder (High) 4-Bit Transparent Latch/4-to-16 Line Decoder (Low) 8-Bit Addressable Latch/1-of-8 Decoder BCD-to-Decimal Decoder/Binary-to-Octal Decoder Binary to 1-4 Decoder (Low) Binary to 1-8 Decoder, (High) Binary to 1-8 Decoder, (Low) Dual 1-of-4 Decoder Dual 1-of-4 Decoder Open-Collector
CMOS CMOS TTL CMOS CMOS CMOS CMOS ECL ECL ECL ECL ECL TTL TTL
Logic: Standard, Special and Programmable
3.1-16
Motorola Master Selection Guide
Selection by Function
Description
DECODER/DEMULTIPLEXERS
Tech. CMOS CMOS TTL MC74AC139
Device(s) - - - MC74HC139A SN74LS139 - - - - - - -
Pins 16 16 16 16 16 16 16 16 16 16 16 16
DIP N N N N,J N,J P,L P,L P,L P P
SM D D D D D FN FN FN D D D,DT D,M, SD,DT
Dual 1-of-4 Decoder/Demultiplexer
MC74ACT139 MC74F139 MC54HC139A SN54LS139 MC10H172 MC10172 MC10H171 MC14555B MC14556B MC74LCX138 MC74LVQ138
Dual 1-of-4 Decoder/Demultiplexer Dual Binary to 1-4 Decoder (High) Dual Binary to 1-4 Decoder (Low) Dual Binary to 1-of-4 Decoder (Active High Outputs) Dual Binary to 1-of-4 Decoder (Active Low Outputs) Low-Voltage CMOS 1-of-8 Decoder/Demultiplexer With 5V Tolerant Inputs and Outputs Low-Voltage Quiet CMOS 1-of-8 Decoder/Demultiplexer
DETECTORS
CMOS TTL ECL ECL ECL CMOS CMOS CMOS CMOS
Analog Mixer Phase-Frequency Detector
ECL ECL ECL ECL ECL
MC12002 MC4044 MC4344 MC12040 MCH12140 SN54LS48 MC14558B SN54LS47 SN54LS247 SN54LS248 SN54LS249 MC74HC4511 MC14511B MC14543B MC14544B MC14513B MC14547B MC10EL32 MC100LVEL32 MC10EL33 MC100LVEL33 MC10EL89 MC10SX1130 MC10163 MC10193 SN54LS147 MC14532B
- - - - MCK12140 SN74LS48 - SN74LS47 SN74LS247 SN74LS248 SN74LS249 - - - - - - MC100EL32 - MC100EL33 - - - - - SN74LS147 -
14 14 14 14 8 16 16 16 16 16 16 16 16 16 18 18 16 8 8 8 8 8 16 16 16 16 16
P,L P,L P,L P,L FN D N,J P,L N,J N,J N,J N,J N P,L P,L P,L P P,L DW D D D D D D P,L P,L N,J P,L D D D D D D D D D D,DW D D
DISPLAY DECODE DRIVERS
BCD-to-Seven Segment Decoder BCD-to-Seven Segment Decoder/Driver
TTL CMOS TTL TTL TTL TTL
BCD-to-Seven Segment Latch/Decoder/Display Driver BCD-to-Seven Segment Latch/Decoder/Driver BCD-to-Seven Segment Latch/Decoder/Driver for Liquid Crystals BCD-to-Seven Segment Latch/Decoder/Driver With Ripple g pp Blanking High Current BCD-to-Seven Segment Decoder/Driver
DIVIDERS
CMOS CMOS CMOS CMOS CMOS CMOS ECL ECL ECL ECL
/ 2 Divider / 4 Divider
DRIVER
Coaxial Cable Driver 300MBit/s LED Driver for FDDI and Fibre Channel
EDACs
ECL ECL ECL ECL TTL CMOS
Error Detection-Correction Circuit (IBM Code) Error Detection-Correction Circuit (Motorola Code)
ENCODERS
10-Line to 4-Line Priority Encoder 8-Bit Priority Encoder
Motorola Master Selection Guide
3.1-17
Logic: Standard, Special and Programmable
Selection by Function
Description
ENCODERS
Tech. TTL ECL ECL SN54LS348 MC10H165 MC10165 SN54LS848 MC74F148 SN54LS148 SN54LS748
Device(s) SN74LS348 - - SN74LS848 - SN74LS148 SN74LS748 - - - - - - - - - - - -
Pins 16 16 16 16 16 16 16 16 28 14 14 14 14 14 14 160, 224 229 84, 128 84, 128, 160, 181
DIP N,J P,L P,L N,J N N,J N,J N
SM D FN FN D D D D D FN
8-Input Priority Encoder
8-Input Priority Encoder (Glitchless) 8-Line to 3-Line Priority Encoder
TTL TTL TTL TTL
Decimal-to-BCD Encoder
ENCODER/DECODERS
CMOS ECL HTL HTL HTL HTL DTL DTL
MC74HC147 MC100SX1230 MC669 MC660 MC661 MC662 MC844 MC944 MPA1064 MPA1100 MPA1016 MPA1036
CMI Encoder/Decoder
EXPANDERS
Dual 4-Iput Expander Expandable Dual 4-Input Gate (Active Pullup) Expandable Dual 4-Input Gate (Passive Pullup) Expandable Dual 4-Input Line Driver Expandable Dual Power Gate
FIELD PROGRAMMABLE GATE ARRAY
P,L P,L P,L P,L P,L P,L DH, KE HV FN, DD FN, DD, DH, HI
14,200-Gate Programmable Array With Up to 160 User I/Os 22,000-Gate Programmable Array With Up to 200 User I/Os 3,500-Gate Programmable Array With Up to 80 User I/Os 8,000-Gate Programmable Array With Up to 120 User I/Os
CMOS CMOS CMOS CMOS
FLIP-FLOPS
3-Bit Differential Flip-Flop 4-Bit D Flip-Flop Individual Clock, Reset Differential Output 4-Bit D Flip-Flop With Enable 4-Bit D-Type Register With With 3-State Outputs 5-Bit Differential Register 6-Bit 2:1 Mux-Register With Common Clock, Asynchronous Master Reset Single Ended 6-Bit D Register With Common Clock, Asynchronous Master Reset, Differential Outputs 6-Bit D Register, With Differential Inputs, (Data & Clock) , VBB, Common Reset 6-Bit Parallel D Register With Enable 9-Bit Hold Register, 700MHz, With Asynchronous Master Reset Clocked Flip-Flop Clocked Flip-Flop D Flip-Flop With Set & Reset Differential Clock D Flip-Flop Differential Data & Clock D Flip-Flop Dual D Flip-Flop
ECL ECL TTL TTL ECL ECL ECL ECL CMOS CMOS ECL DTL DTL ECL ECL ECL ECL CMOS CMOS CMOS
MC10E431 MC10E131 SN54LS379 SN54LS173A MC10E452 MC10E167 MC10E151 MC10E451 MC74AC378 MC74ACT378 MC10E143 MC845 MC945 MC10EL31 MC10EL51 MC100LVEL51 MC10EL52 MC74AC74 MC74ACT74 MC14013B
MC100E431 MC100E131 SN74LS379 SN74LS173A MC100E452 MC100E167 MC100E151 MC100E451 - - MC100E143 - - MC100EL31 MC100EL51 - MC100EL52 - - -
28 28 16 16 28 28 28 28 16 16 28 14 14 8 8 8 8 14 14 14 N N P,L P,L P,L N N N,J N,J
FN FN D D FN FN FN FN D D FN
D D D D D D D
Logic: Standard, Special and Programmable
3.1-18
Motorola Master Selection Guide
Selection by Function
Description
FLIP-FLOPS
Tech. CMOS CMOS
Device(s) MC54HC74A MC74VHC74 MC74HCT74A MC74F74 SN54LS74A MC100LVEL29 SN54LS112A SN54LS113A SN54LS114A SN54LS109A MC663 SN54LS107A MC952 MC953 MC74AC112 MC74ACT112 MC74AC113 MC74ACT113 SN54LS76A MC74HC112 MC14027B MC74HC73 MC74HC107 MC74HC76 MC10135 MC10H135 MC74F112 SN54LS73A MC74AC109 MC74ACT109 MC74HC109 MC74F109 MC10131 MC10H131 SN54LS174 MC14174B SN54LS378 MC74AC174 MC74F174 MC74ACT174 MC54HC174A MC74HCT174A MC10H176 MC10176 MC10H186 MC10186 MC10231 MC10EL35 MC74HC74A - - - SN74LS74A MC100EL29 SN74LS112A SN74LS113A SN74LS114A SN74LS109A - SN74LS107A - - - - - - SN74LS76A - - - - - - - - SN74LS73A - - - - - - SN74LS174 - SN74LS378 - - - MC74HC174A - - - - - - MC100EL35
Pins 14 14 14 14 16 20 16 14 14 16 14 14 14 14 16 16 14 14 16 16 16 14 14 16 16 16 16 14 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 8
DIP N,J
SM D,DT D, DT,M
Dual D Flip-Flop With Set and Reset
Dual D Flip-Flop With Set and Reset With LSTTL Compatible Inputs Dual D-Type Positive Edge-Triggered Flip-Flop Dual Differential Data and Clock D Flip-Flop With Set and Reset Dual J-K Negative Edge-Triggered Flip-Flop
CMOS TTL TTL ECL TTL TTL TTL
N N N,J N,J N,J N,J N,J P,L N,J P,L P,L N N N N N,J N P,L N N N P,L P,L N N,J N N N N P,L P,L N,J P,L N,J N N N N,J N P,L P,L P,L P,L P,L
D D D DW D D D D D
Dual J-K Positive Edge-Triggered Flip-Flop Dual J-K Flip-Flop Dual J-K Flip-Flop (Common Clock and CD Separate SD) Dual J-K Flip-Flop (Separate Clock and SD, No CD) Dual J-K Flip-Flop Negative Edge Trigger Dual J-K Flip-Flop Negative Edge Trigger Dual J-K Flip-Flop With Set and Clear Dual J-K Flip-Flop With Set and Reset Dual J-K Flip-Flop Dual J-K Flip-Flop With Reset Dual J-K Flip-Flop With Set and Reset Dual J-K Master-Slave Flip-Flop Dual J-K Negative Edge-Triggered Flip-Flop Dual J-K Positive Edge-Triggered Flip-Flop With Set & Clear Dual J-K Flip-Flop With Set and Reset Dual J-K Positive Edge-Triggered Flip-Flop Dual Type-D Master-Slave Flip-Flop Hex D Flip-Flop Hex D Flip-Flop With Enable Hex D Flip-Flop With Master Reset
TTL HTL TTL DTL DTL CMOS CMOS CMOS CMOS TTL CMOS CMOS CMOS CMOS CMOS ECL ECL TTL TTL CMOS CMOS CMOS TTL ECL ECL TTL CMOS TTL CMOS TTL CMOS
D D D D D D,DT D D D D FN FN D D D D D D FN FN D D D D D D D D FN FN FN FN FN D
Hex D Flip-Flop With Common Clock & Reset Hex D Master-Slave Flip-Flop Hex D Master-Slave Flip-Flop With Reset High Speed Dual D Master-Slave Flip-Flop J-K Flip-Flop
CMOS CMOS ECL ECL ECL ECL ECL ECL
Motorola Master Selection Guide
3.1-19
Logic: Standard, Special and Programmable
Selection by Function
Description
FLIP-FLOPS
Tech. CMOS CMOS CMOS CMOS ECL CMOS CMOS ECL HTL CMOS CMOS TTL CMOS CMOS TTL TTL CMOS CMOS CMOS CMOS TTL TTL CMOS CMOS TTL TTL CMOS CMOS MC74LCX74
Device(s) - - - - - - - - - MC74HC534A MC74HCT374A - - - - SN74LS273 - - MC74HC273A - - SN74LS377 - - - SN74LS374 - - - - - - - MC74HC374A - MC74HC574A - MC74HCT574A - - -
Pins 14 20 20 20 8 20 20 16 14 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 16 16 16
DIP
SM D,DT DW,M, DT DW,M, DT DW,M, DT D DW,M, SD,DT DW,M, SD,DT
Low-Voltage CMOS Octal D-Type Flip-Flop With Set and Reset, 3-State, Non-Inverting With 5V Tolerant Inputs Low-Voltage CMOS 16-Bit D-Type Flip-Flop, 3-State, Non-Inverting With 5V Tolerant Inputs and Outputs Low-Voltage CMOS Octal D-Type Flip-Flop, 3-State, Non-Inverting With 5V Tolerant Inputs and Outputs Low-Voltage CMOS Octal D-Type Flip-Flop Flow Through Pinout, 3-State, Non-Inverting With 5V Tolerant Inputs and Outputs Low Voltage D Flip-Flop With Set & Reset Low-Voltage Quiet CMOS Octal D-Type Flip-Flop Low-Voltage Quiet CMOS Octal D-Type Flip-Flop Flow Through Pinout Master-Slave Flip-Flop Master-Slave R-S Flip-Flop Octal 3-State Inverting D Flip-Flop Octal 3-State Non-Inverting D Flip-Flop With LSTTL Compatible Inputs Octal D Flip Flop, With 3-State Outputs Octal D Flip-Flop Octal D Flip-Flop With 3-State Outputs/Broadside Pinout, F374 Octal D Flip-Flop With Clear Octal D Flip-Flop With Clock Enable Octal D Flip-Flop With Common Clock & Reset Octal D Flip-Flop With Common Clock and Reset With LSTTL Compatible Inputs Octal D Flip-Flop With Enable Octal D Flip-Flop With Enable/ Non-Inverting Octal D Type Flip-Flop With 3-State Outputs
MC74LCX16374 MC74LCX374 MC74LCX574 MC100LVEL31 MC74LVQ374 MC74LVQ574 MC1670 MC664 MC54HC534A MC54HCT374A MC74F374 MC74AC273 MC74ACT273 MC74F574 SN54LS273 MC74AC377 MC74ACT377 MC54HC273A MC74HCT273A MC74F377 SN54LS377 MC74AC374 MC74ACT374 MC74F534 SN54LS374 MC74AC534 MC74ACT534 MC74AC564 MC74ACT564 MC74AC574 MC74ACT574 MC74HC564A MC54HC374A MC74VHC374 MC54HC574A MC74VHC574 MC54HCT574A MC74AC175 MC74ACT175 MC74F175
L P,L N,J N,J N N N N N,J N N N,J N N N,J N N N N,J N N N N N N N N,J DW DW, SD,DT DW DW DW DW DW DW DW DW, DT DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW, SD,DT DW, DT,M N,J DW DW, DT,M N,J N N N DW D D D
Octal D-Type Latch With 3-State Outputs
CMOS CMOS CMOS CMOS
Octal With 3-State Outputs Inverting D Flip-Flop Octal With 3-State Outputs Non-Inverting D Flip-Flop
CMOS CMOS CMOS CMOS CMOS
Octal With 3-State Outputs Non-Inverting D Flip-Flop With LSTTL Compatible Inputs Quad D Flip-Flop
CMOS CMOS CMOS TTL
Logic: Standard, Special and Programmable
3.1-20
Motorola Master Selection Guide
Selection by Function
Description
FLIP-FLOPS
Tech. TTL CMOS CMOS CMOS CMOS TTL CMOS ECL CMOS TTL CMOS TTL CMOS SN54LS175 MC14175B
Device(s) SN74LS175 - MC74HC175 MC74HC175A - - - MC100EL30 - SN74LS133 - SN74LS30 - - SN74LS21 - - SN74LS40 - - - - SN74LS20 SN74LS22 - - - - - - - - - - MC74HC08A - SN74LS08 SN74LS09 - - - MC74HCT08A - SN74LS26 SN74LS37
Pins 16 16 16 16 16 16 16 20 16 16 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 16 14 14 14 14 14 14 14 14 14 14 16 16 14 14 14 14 14
DIP N,J P,L N,J N,J P,L N N
SM D D D D,SD D D D DW
Quad D Flip-Flop Quad D Flip-Flop With Common Clock & Reset Quad D-Type Register With 3-State Outputs Quad Parallel Register With Enable Quad With 3-State Outputs D Flip-Flop With Common Clock & Reset Triple D Flip-Flop With Set and Reset
GATES, AND/NAND
MC54HC175 MC54HC175A MC14076B MC74F379 MC74HC173 MC100LVEL30 MC74HC133 SN54LS133 MC74HC30 SN54LS30 MC14068B MC74F21 SN54LS21 MC14082B MC74F40 SN54LS40 MC74AC20 MC74ACT20 MC74F20 MC74HC20 SN54LS20 SN54LS22 MC14012B MC14012UB MC830 MC10197 MC74LCX08 MC74LCX00 MC74LVQ00 MC74AC08 MC74ACT08 MC74F08 MC54HC08A MC74VHC08 SN54LS08 SN54LS09 MC10H104 MC10104 MC14081B MC54HCT08A MC74F37 SN54LS26 SN54LS37
13-Input NAND Gate 8-Input NAND Gate
N N,J N N,J P N N,J P,L N N,J N N N N N,J N,J P,L P,L P,L P,L
D D D D D D D D D D D D D D D D D D FN D,DT D,DT D,M, DT,SD
Dual 4-Input AND Gate
TTL TTL CMOS
Dual 4-Input NAND Buffer Dual 4-Input NAND Gate
TTL TTL CMOS CMOS TTL CMOS TTL TTL CMOS
Dual 4-Input NAND Gate (Unbuffered) Expandable NAND Gate Hex AND Gate Low-Voltage CMOS Quad 2-Input AND Gate, 5V-Tolerant Inputs Low-Voltage CMOS Quad 2-Input NAND Gate, 5V-Tolerant Inputs Low-Voltage Quiet CMOS Quad 2-Input NAND Gate Quad 2-Input AND Gate
CMOS DTL ECL CMOS CMOS CMOS CMOS CMOS TTL CMOS CMOS TTL TTL ECL ECL CMOS
N N N N,J
D D D D,DT D, DT,M
N,J N,J P,L P,L P,L N,J N N,J N,J
D D FN FN D D D D D
Quad 2-Input AND Gate With LSTTL-Compatible Inputs Quad 2-Input NAND Buffer
CMOS TTL TTL TTL
Motorola Master Selection Guide
3.1-21
Logic: Standard, Special and Programmable
Selection by Function
Description
GATES, AND/NAND
Tech. TTL TTL DTL DTL CMOS CMOS TTL CMOS CMOS TTL TTL TTL CMOS MC74F38 SN54LS38 MC846 MC946 MC74AC00
Device(s) - SN74LS38 - - - - - MC74HC00A - SN74LS00 SN74LS01 SN74LS03 - - MC74HCT00A - - - - - SN74LS11 SN74LS15 - - - - - SN74LS10 SN74LS12 - - MC100EL04 MC100EL05 - MC100EL07 - - SN74LS55 SN74LS54 - - MC100EL01 - - - -
Pins 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 8 8 8 8 14 14 14 14 14 16 8 8 16 16 16
DIP N N,J P,L P,L N N N N,J
SM D D
Quad 2-Input NAND Buffer Open-Collector Quad 2-Input NAND Buffer Open-Collector Quad 2-Input NAND Gate
D D D D,DT D, DT,M
MC74ACT00 MC74F00 MC54HC00A MC74VHC00 SN54LS00 SN54LS01 SN54LS03 MC14011B MC14011UB MC54HCT00A MC74HC03A MC74AC11 MC74ACT11 MC74F11 MC74HC11 SN54LS11 SN54LS15 MC14073B MC74AC10 MC74ACT10 MC74F10 MC74HC10 SN54LS10 SN54LS12 MC14023B MC14023UB MC10EL04 MC10EL05 MC100LVEL05 MC10EL07 MC74HC51 MC74HC58 SN54LS55 SN54LS54 MC74F64 MC14519B MC10EL01 MC100LVEL01 MC10H119 MC10H121 MC10121
N,J N,J N,J P,L P,L N,J N N N N N N,J N,J P,L N N N N N,J N,J P,L P,L
D D D D D D D,DT D D D D D D D D D D D D D D D D D D D
Quad 2-Input NAND Gate (Unbuffered) Quad 2-Input NAND Gate With LSTTL-Compatible Inputs Quad 2-Input NAND Gate With Open-Drain Outputs Triple 3-Input AND Gate
CMOS CMOS CMOS CMOS CMOS TTL CMOS TTL TTL CMOS
Triple 3-Input NAND Gate
CMOS CMOS TTL CMOS TTL TTL CMOS
Triple 3-Input NAND Gate (Unbuffered)
GATES, COMPLEX
CMOS ECL ECL ECL ECL CMOS CMOS TTL TTL TTL CMOS ECL ECL ECL ECL ECL
2-Input AND/NAND Gate 2-Input Differential AND/NAND Gate 2-Input XOR/NOR Gate 2-Wide, 2-Input/2-Wide, 3-Input AND-NOR Gate 2-Wide, 2-Input/2-Wide, 3-Input AND-OR Gate 2-Wide, 4-Input AND/OR Invert Gate 3-2-2-3-Input AND/OR Invert Gate 4-2-3-2 Input AND-OR-Invert Gate 4-Bit AND/OR Selector 4-Input OR/NOR Gate 4-Wide 4-3-3-3 Input OR-AND Gate 4-Wide OR-AND/OR-AND-Invert Gate 4-Wide OR-AND/OR-AND-Invert Gate
N N N,J N,J N P
D D D D D D D D
P,L P,L P,L
FN FN FN
Logic: Standard, Special and Programmable
3.1-22
Motorola Master Selection Guide
Selection by Function
Description
GATES, COMPLEX
Tech. CMOS TTL ECL ECL TTL ECL ECL ECL ECL
Device(s) MC74HC4078 SN54LS51 MC10117 MC10H117 MC74F51 MC10H118 MC10H109 MC10109 MC10H209 MC14501UB MC1660 MC14530B MC14506UB MC14572UB MC10212 MC10E101 MC10E404 MC10H101 MC10101 MC10E104 MC10E107 MC10H105 MC10105 MC10H107 MC10107 MC74LCX86 MC74AC810 MC74ACT810 MC74HC7266 MC74HC7266A SN54LS266 MC14077B MC74AC86 MC74ACT86 MC74F86 MC54HC86 MC54HC86A SN74LS136 SN54LS386 SN54LS86 MC10H113 MC10113 MC14070B MC1672 - SN74LS51 - - - - - - - - - - - - - MC100E101 MC100E404 - - MC100E104 MC100E107 - - - - - - - - - SN74LS266 - - - - MC74HC86 MC74HC86A - SN74LS386 SN74LS86 - - - -
Pins 14 14 16 16 14 16 16 16 16 16 16 16 16 16 16 28 28 16 16 28 28 16 16 16 16 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 16 16 14 16
DIP N N,J P,L P,L N P,L P,L P,L P,L P L P L P P
SM D D FN FN D FN FN FN FN D
8-Input NOR/OR Gate Dual 2 Wide 2-Input/3-Input AND/OR Invert Gate Dual 2-Wide 2-3-Input OR-AND/OR-AND-Invert Gate Dual 2-Wide 2-Input, 2-Wide 3-Input AND-OR-Invert Gate Dual 2-Wide 3-Input OR-AND Gate Dual 4-5 Input OR/NOR Gate
Dual 4-Input NAND, 2-Input NOR/OR, 8-Input AND/NAND Gate (Unbuffered) Dual 4-Input OR/NOR Gate Dual 5-Input Majority Logic Gate Dual Expandable AND OR Invert Gate (Unbuffered) Hex NAND/NOR/Invert Gate (Unbuffered) High Speed Dual 3-Input 3-Output OR/NOR Gate Quad 4-Input OR/NOR Gate Quad Differential AND/NAND Gate Quad OR/NOR Gate Quint 2-Input AND/NAND Gate Quint 2-Input XOR/XNOR Gate Triple 2-3-2 Input OR/NOR Gate Triple 2-Input Exclusive OR/Exclusive NOR Gate
GATES, EXCLUSIVE OR/EXCLUSIVE NOR
CMOS ECL CMOS CMOS CMOS ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL
D D FN FN
P,L P,L
FN FN FN FN
P,L P,L P,L P,L
FN FN FN FN D,M SD,DT
Low-Voltage CMOS Quad 2-Input Exclusive OR Gate With 5V Tolerant Inputs Quad 2-Input Exclusive NOR Gate
CMOS CMOS CMOS CMOS CMOS TTL
N N N N N,J P,L N N N N,J N,J N,J N,J N,J P,L P,L P,L L
DW DW D D,DT D D D D D D D,DT D D D FN FN D
Quad Exclusive NOR Gate Quad 2-Input Exclusive OR Gate
CMOS CMOS CMOS TTL CMOS CMOS TTL TTL
Quad Exclusive OR Gate
TTL ECL ECL CMOS
Triple 2-Input Exclusive-OR Gate
ECL
Motorola Master Selection Guide
3.1-23
Logic: Standard, Special and Programmable
Selection by Function
Description
GATES, NOR
Tech. CMOS ECL ECL ECL MC14078B MC10111 MC10H211 MC10211
Device(s) - - - - - - - SN74LS260 - SN74LS28 SN74LS33 - - - MC74HC02A - SN74LS02 - - - - - - MC74HC27 SN74LS27 - - - - - - - - - - - - - MC74HC32A - MC74HCT32A SN74LS32 - - -
Pins 14 16 16 16 14 14 14 14 14 14 14 14 14 14 14 14 14 16 16 16 14 14 16 14 14 14 14 16 16 16 16 16 14 14 14 14 14 14 14 14 14 14 16 16 14
DIP P P,L P,L P,L N P,L P,L N,J N,J N,J N N N N,J
SM D FN FN FN D D D D D,DT D D D D D D,DT D, DT,M
8-Input NOR Gate Dual 3-Input 3-Output NOR Gate
Dual 4-Input NOR Gate Dual 4-Input NOR Gate (Unbuffered) Dual 5-Input NOR Gate Low-Voltage CMOS Quad 2-Input NOR Gate, 5V-Tolerant Inputs Quad 2-Input NOR Buffer Quad 2-Input NOR Gate
CMOS CMOS CMOS TTL CMOS TTL TTL CMOS CMOS TTL CMOS CMOS TTL ECL ECL ECL CMOS
MC74HC4002 MC14002B MC14002UB SN54LS260 MC74LCX02 SN54LS28 SN54LS33 MC74AC02 MC74ACT02 MC74F02 MC54HC02A MC74VHC02 SN54LS02 MC10H102 MC10102 MC1662 MC14001B MC14001UB MC10H100 MC54HC27 SN54LS27 MC14025B MC14025UB MC10H106 MC10106 MC10110 MC10H210 MC10210 MC14072B MC74LCX32 MC74LVQ32 MC74AC32 MC74ACT32 MC74F32 MC54HC32A MC74VHC32 MC54HCT32A SN54LS32 MC10H103 MC10103 MC14071B
N,J P,L P,L L P,L P,L P,L N,J N,J P,L P,L P,L P,L P,L P,L P,L P
D FN FN D D FN D D D D FN FN FN FN FN D D,DT D,M SD,DT
Quad 2-Input NOR Gate (Unbuffered) Quad 2-Input NOR Gate With strobe Triple 3-Input NOR Gate
CMOS ECL CMOS TTL CMOS
Triple 3-Input NOR Gate (Unbuffered) Triple 4-3-3 Input NOR Gate
GATES, OR
CMOS ECL ECL
Dual 3-Input 3-Output OR Gate
ECL ECL ECL
Dual 4-Input OR Gate Low-Voltage CMOS Quad 2-Input OR Gate, 5V-Tolerant Inputs Low-Voltage Quiet CMOS Quad 2-Input OR Gate, 5V-Tolerant Inputs Quad 2-Input OR Gate
CMOS CMOS CMOS CMOS CMOS TTL CMOS CMOS CMOS TTL ECL ECL CMOS
N N N N,J
D D D D,DT D, DT,M
N,J N,J P,L P,L P,L
D D FN FN D
Logic: Standard, Special and Programmable
3.1-24
Motorola Master Selection Guide
Selection by Function
Description
GATES, OR
Tech. CMOS CMOS
Device(s) MC74HC4075 MC14075B MC14500B MC836 MC837 MC936 MC937 MC840 MC10E122 MC10EL12 MC100LVEL12 MC14007UB MC10H188 MC10188 MC14050B MC74AC04 MC74ACT04 MC74F04 MC54HC04A MC74VHC04 SN54LS04 SN54LS05 MC14069UB MC10H189 MC10189 MC74HCT04A MC74AC05 MC74ACT05 MC677 MC678 MC10195 MC14049B MC14049UB MC54HC4049 MC54HC4050 MC74HCU04 MC74HCU04A MC74LCX04 MC74LVQ04 MC672 MC668 MC10E112 MC14502B MC671 MC670 - - - - - - - - MC100E122 MC100EL12 - - - - - - - - MC74HC04A - SN74LS04 SN74LS05 - - - - - - - - - - - MC74HC4049 MC74HC4050 - - - - - - MC100E112 - - -
Pins 14 14 16 14 14 14 14 14 28 8 8 14 16 16 16 14 14 14 14 14 14 14 14 16 16 14 14 14 14 14 16 16 16 16 16 14 14 14 14 14 14 28 16 14 14
DIP N P,L P P P P,L P,L P
SM D D DW
Triple 3-Input OR Gate
INDUSTRIAL CONTROL UNIT
Industrial Control Unit
INVERTERS
CMOS DTL DTL DTL DTL
Hex Inverter
Hex Inverter (Without Input Diodes)
INVERTER/BUFFERS, 2-STATE
DTL ECL ECL ECL CMOS ECL ECL CMOS CMOS CMOS TTL CMOS CMOS TTL TTL
9-Bit Buffer Driver Dual Complementary Pair Plus Inverter (Unbuffered) Hex Buffer With Enable Hex Buffer/Non-Inverting Hex Inverter
FN D D P P,L P,L P,L N N N N,J D FN FN D D D D D,SD, DT D, DT,M N,J N,J P,L P,L P,L N N N P,L P,L P,L P P,L N,J N,J N N FN D D D D D D,DT D,DT D,M, SD,DT P,L P,L FN P,L P,L P,L DW D D D FN FN D,DT D D
Hex Inverter Gate (Unbuffered) Hex Inverter With Enable Hex Inverter With LSTTL Compatible Inputs Hex Inverter With open Drain Outputs Hex Inverter With Strobe (Active Pullup) Hex Inverter With Strobe (Without Output Resistors) Hex Inverter/Buffer Hex Inverter/Buffer (Unbuffered) Hex Inverting Buffer/Logic-Level Down Converter Hex Non-Inverting Buffer/Logic-Level Down Converter Hex Unbuffered Inverter Low-Voltage CMOS Hex Inverter, With 5V-Tolerant Inputs Low-Voltage Quiet CMOS Hex Inverter Quad 2-Input Gate (Active Pullup) Quad 2-Input Gate (Passive Pullup) Quad Driver Strobed Hex Inverter/Buffer Triple 3-Input Gate (Active Pullup) Triple 3-Input Gate (Passive Pullup)
CMOS ECL ECL CMOS CMOS CMOS HTL HTL ECL CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS HTL HTL ECL CMOS HTL HTL
Motorola Master Selection Guide
3.1-25
Logic: Standard, Special and Programmable
Selection by Function
Description
LATCHES
Tech. ECL ECL TTL TTL TTL MC10E256 MC10E156 SN54LS75 SN54LS77 SN54LS375 MC10E154 MC10E155 MC10E150 MC74AC259
Device(s) MC100E256 MC100E156 SN74LS75 SN74LS77 SN74LS375 MC100E154 MC100E155 MC100E150 - - - SN74LS259 - - - MC100E175 - - - - - - - - - - -
Pins 28 28 16 14 16 28 28 28 16 16 16 16 16 18 18 28 16 16 16 16 16 16 24 16 20 48 20
DIP
SM FN FN
3-Bit 4:1 Mux-Latch (Integrated E156 & E171) 3-Bit 4:1 Mux-Latch, With Common Enable, Asynchronous Master Reset, Differential Output 4-Bit D Latch
N,J N,J N,J
D D D FN FN FN
5-Bit 2:1 Mux-Latch, With Common Enable, Asynchronous Master Reset Differential Output 6-Bit 2:1 Mux-Latch, With Common Enable, Asynchronous Master Reset Single Ended 6-Bit D Latch 8-Bit Addressable Latch
ECL ECL ECL CMOS CMOS TTL TTL CMOS CMOS
N N N N,J P P P,L
D D D D DW
MC74ACT259 MC74F259 SN54LS259 MC14099B MC14599B MC14598B MC10E175 MC10H130 MC74HC75 MC74AC256 MC74ACT256 MC74F256 SN54LS256 MC14508B MC10130 MC74LCX373
MC74LCX16373
8-Bit Bus Compatible Addressable Latch 9-Bit Latch, With Parity Dual Latch Dual 2-Bit Transparent Latch Dual 4-Bit Addressable Latch
CMOS ECL ECL CMOS CMOS CMOS TTL TTL
FN P,L N N N N N,J P,L P,L FN D DW DW D D DW FN DW,M, DT DT DW,M, SD,DT DW,M, SD,DT DW,M, SD,DT N,J N N N N N N N,J N N N N DW, SD,DT DW DW DW DW DW DW DW DW DW DW DW
Dual 4-Bit Latch Dual Latch Low-Voltage CMOS Octal Transparent Latch, 3-State, Non-Inverting With 5V Tolerant Inputs and Outputs Low-Voltage CMOS 16-Bit Transparent Latch, 3-State, Non-Inverting With 5V Tolerant Inputs and Outputs Low-Voltage CMOS Octal Transparent Latch Flow Through Pinout, 3-State, Non-Inverting With 5V Tolerant Inputs and Outputs Low-Voltage Quiet CMOS Octal Transparent Latch Low-Voltage Quiet CMOS Octal Transparent Latch Flow Through Pinout Octal 3-State Non-Inverting Transparent Latch With LSTTL Compatible Inputs Octal D Latch With 3-State Outputs
CMOS ECL CMOS CMOS CMOS
MC74LCX573
CMOS CMOS CMOS CMOS CMOS CMOS CMOS
MC74LVQ373 MC74LVQ573 MC54HCT373A MC74AC563 MC74ACT563 MC74AC573 MC74ACT573 MC74AC373 MC74ACT373 SN54LS373 MC74F373 MC74F533 MC74AC533 MC74ACT533
- - MC74HCT373A - - - - - - SN74LS373 - - - -
20 20 20 20 20 20 20 20 20 20 20 20 20 20
Octal Transparent Latch With 3-State Outputs
CMOS CMOS TTL TTL TTL CMOS CMOS
Logic: Standard, Special and Programmable
3.1-26
Motorola Master Selection Guide
Selection by Function
Description
LATCHES
Tech. CMOS CMOS CMOS CMOS CMOS CMOS
Device(s) MC54HC533A MC54HC563A MC54HC373A MC74VHC373 MC54HC573A MC74VHC573 MC74HCT573A MC10133 MC10153 MC14044B MC14043B SN54LS279 MC14042B MC10H175 MC10175 MC10H660 MC10E197 MC74AC151 MC74ACT151 MC14067B MC10E164 MC10E163 MC10EL58 MC10E171 MC10EL57 MC10E158 MC54HC4351 MC54HC4051 MC14051B MC14512B MC74HC151 MC54HC251 MC74F151 SN54LS151 SN54LS251 MC74F251 MC74AC251 MC74ACT251 MC54HC354 MC10H164 MC10164 MC74HC4851A MC74HC4853A MC74HC533A MC74HC563A MC74HC373A - MC74HC573A - - - - - - SN74LS279 - - - MC100H660 - - - - MC100E164 MC100E163 MC100EL58 MC100E171 MC100EL57 MC100E158 MC74HC4351 MC74HC4051 - - - MC74HC251 - SN74LS151 SN74LS251 - - - MC74HC354 - - MC74HC4852A -
Pins 20 20 20 20 20 20 20 16 16 16 16 16 16 16 16 28 28 16 16 24 28 28 8 28 16 28 20 16 16 16 16 16 16 16 16 16 16 16 20 16 16 16
DIP N,J N,J N,J
SM DW
DW,DT
Octal With 3-State Outputs Inverting Transparent Latch Octal With 3-State Outputs Non-Inverting Transparent Latch
DW, DT,SD DW, DT,M
N,J
DW DW, DT,M
Octal With 3-State Outputs Non-Inverting Transparent Latch With LSTTL Compatible Inputs Quad Latch Quad NAND R-S Latch Quad NOR R-S Latch Quad Set/Reset Latch Quad Transparent Latch Quint Latch
MEMORY SUPPORT
CMOS ECL ECL CMOS CMOS TTL CMOS ECL ECL
N P,L P,L P P,L N,J P,L P,L P,L
DW FN FN D D D D FN FN FN FN
4-Bit ECL-TTL Load Reducing DRAM Driver
MISCELLANEOUS
ECL ECL CMOS CMOS CMOS ECL ECL ECL ECL ECL ECL CMOS CMOS CMOS
Data Separator
MULTIPLEXER/DATA SELECTORS
1-of-8 Decoder/Demultiplexer 16-Channel Analog Multiplexer/Demultiplexer 16:1 Multiplexer 2-Bit 8:1 Multiplexer 2:1 Multiplexer 3-Bit 4:1 Multiplexer, With Split Select Differential Output 4:1 Differential Multiplexer 5-Bit 2:1 Multiplexer, With Differential Output 8-Channel Analog Multiplexer/Demultiplexer With Address Latch 8-Channel Analog Multiplexer/Demultiplexer
N N P
D D DW FN FN D FN D FN
N,J N,J P,L P,L N N,J N N,J N,J N N N N,J P,L P,L N
DW D, DW ,DT D D D D D D D D D D DW FN FN D,DW, DT
8-Channel Data Selector 8-Input Data Selector/Multiplexer 8-Input Data Selector/Multiplexer With 3-State Outputs 8-Input Multiplexer 8-Input Multiplexer With 3-State Outputs
CMOS CMOS CMOS TTL TTL TTL TTL CMOS CMOS
8-Input Data Selector/Multiplexer With Data and Address Latchs and With 3-State Outputs 8-Line Multiplexer Analog Multiplexer/Demultiplexer With Injection Current Effect g p p j Control Automotive Customized Control,
CMOS ECL ECL CMOS
Motorola Master Selection Guide
3.1-27
Logic: Standard, Special and Programmable
Selection by Function
Description
MULTIPLEXER/DATA SELECTORS
Tech. CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS TTL TTL TTL TTL MC14529B
Device(s) - - - - - - - - - - - - SN74LS153 SN74LS352 - - - - SN74LS253 SN74LS353 - - - - MC100EL56 - - - - - MC74HC158 - - MC74HC157A - - - - SN74LS157 SN74LS158 - - - - - - SN74LS257B SN74LS298
Pins 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 20 16 32 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16
DIP P N P,L P N N N N N N N N N,J N,J N N N N N,J N,J N N P,L P,L P,L
SM D D, DW D D D D D D DW DW D D D D DW DW D D D D D D FN FN DW FN FA M,D, SD,DT
Dual 4-Channel Analog Data Selector Dual 4-Channel Analog Multiplexer/Demultiplexer Dual 4-Channel Data Selector/Multiplexer Dual 4-Input Data Selector/Multiplexer Dual 4-Input Data Selector/Multiplexer With 3-State Outputs Dual 4-Input Multiplexer
MC74HC4052 MC14052B MC14539B MC74HC153 MC74HC253 MC74AC153 MC74ACT153 MC74AC352 MC74ACT352 MC74F153 MC74F352 SN54LS153 SN54LS352 MC74AC253 MC74ACT253 MC74AC353 MC74ACT353 SN54LS253 SN54LS353 MC74F253 MC74F353 MC10H174 MC10174 MC100LVEL56 MC10134 MC100LVE164 MC74LCX157 MC10H173 MC14551B MC54HC158 MC74HC158A MC74HC257 MC54HC157A MC74VHC157 MC74HCT157A MC74F157A MC74F158A SN54LS157 SN54LS158 MC10159 MC10158 MC74AC258 MC74ACT258 MC74ACT257 MC74AC257 SN54LS257B SN54LS298
Dual 4-Input Multiplexer With 3-State Outputs
CMOS CMOS CMOS CMOS TTL TTL TTL TTL
Dual 4-to-1 Multiplexer Dual Differential 2:1 Multiplexer (3.3V) Dual Multiplexer With Latch Low Voltage 16:1 Multiplexer Low-Voltage CMOS Quad 2-Input, Non-Inverting With 5V Tolerant Inputs and Outputs Quad 2-Input Multiplexer With Latch Quad 2-Channel Analog Multiplexer/Demultiplexer Quad 2-Input Data Selector/Multiplexer Quad 2-Input Data Selector/Multiplexer With 3-State Outputs Quad 2-Input Data Selectors/Multiplexers
ECL ECL ECL ECL ECL CMOS ECL CMOS CMOS CMOS CMOS CMOS CMOS
P,L P N,J N,J N N,J
FN D D D,DT D D,DT D, DT,M
Quad 2-Input Data Selector/Multiplexer With LSTTL Compatible Inputs Quad 2-Input Multiplexer
CMOS TTL TTL TTL TTL
N N N N,J N,J P,L P,L N N N N N,J N,J
D D D D D FN FN DW DW D D D D
Quad 2-Input Multiplexer (Inverting) Quad 2-Input Multiplexer (Non-Inverting) Quad 2-Input Multiplexer Inverting With 3-State Outputs Quad 2-Input Multiplexer Non-Inverting With 3-State Outputs Quad 2-Input Multiplexer With 3-State Outputs Quad 2-Input Multiplexer With Storage
ECL ECL CMOS CMOS CMOS CMOS TTL TTL
Logic: Standard, Special and Programmable
3.1-28
Motorola Master Selection Guide
Selection by Function
Description
MULTIPLEXER/DATA SELECTORS
Tech. CMOS CMOS ECL TTL CMOS CMOS ECL TTL TTL ECL TTL TTL TTL TTL MC74AC158
Device(s) - - - SN74LS258B - - - - - - - - SN74LS398 SN74LS399 MC100E157 - - MC74HC4016 MC74HC4066 - MC74HC4053 - MC74HC4353 - - - - - - - - SN74LS221 MC74HC4538A - - - - SN74LS122 SN74LS123 - - - - -
Pins 16 16 16 16 16 16 16 16 16 16 20 16 20 16 28 14 14 14 14 16 16 16 20 20 20 28 28 20 20 14 16 16 16 16 14 14 16 14 14 16 14 16 14 8
DIP N N P,L N,J N N P,L N N P,L N N N,J N,J P,L P,L N,J N,J N N,J P,L N,J
SM D D FN D D D FN D D FN DW D DW D FN D D D D,DT D D, DW D DW DW DW FN FN
Quad 2-Input Multiplexer, Inverting Quad 2-Input Multiplexer, Inverting Output Quad 2-Input Multiplexer, Inverting, With 3-State Outputs Quad 2-Input Multiplexer, Non-Inverting Quad 2-Input Multiplexer, Non-Inverting Output Quad 2-Input Multiplexer, With 3-State Outputs Quad 2-Input Multiplexer/Latch Quad 2-Port Register
MC74ACT158 MC10H159 SN54LS258B MC74AC157 MC74ACT157 MC10H158 MC74F257A MC74F258A MC10173 MC74F398 MC74F399 SN54LS398 SN54LS399 MC10E157 MC14016B MC14066B MC54HC4016 MC54HC4066 MC74HC4316 MC54HC4053 MC14053B MC54HC4353 MC100EL59 MC100LVEL59 MC100E457 MC10E457 MC12101 MC12100 MC667 MC14528B SN54LS221 MC54HC4538A MC14538B MC4024 MC951 MC10198 SN54LS122 SN54LS123 MC1658 MC74HC4024 MC12061 MC4324 MC12148
Quad 2:1 Mux, Individual-Select Quad Analog Switch/Multiplexer Quad Analog Switch/Multiplexer/Demultiplexer Quad Analog Switch/Multiplexer/Demultiplexer With Separate Analog/Digital Power Supplies Triple 2-Channel Analog Multiplexer/Demultiplexer Triple 2-Channel Analog Multiplexer/Demultiplexer With Address Latch Triple 2:1 Multiplexer Triple 2:1 Multiplexer (3.3V) Triple Differential 2:1 Multiplexer
MULTIVIBRATORS
ECL CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS ECL ECL ECL ECL
130MHz Voltage Controlled Multivibrator 200 MHz Voltage Controlled Multivibrator Dual Monostable Multivibrator Dual Monstable Multivibrators With Schmitt Trigger Inputs Dual Precision Monostable Multivibrator Retriggerable, Resettable) Dual Precision Monostable Multivibrator Dual Voltage-Controlled Multivibrator Monostable Multivibrator Retriggerable Monostable Multivibrators Voltage Controlled Multivibrator
OSCILLATORS
ECL ECL HTL CMOS TTL CMOS CMOS ECL DTL ECL TTL TTL ECL CMOS ECL ECL ECL
P P P,L P,L N,J N,J P,L P,L P,L P,L N,J N,J P,L N P,L P,L
FN FN D D D D, DW
FN D D D,FN D
7-Stage Binary Ripple Counter Crystal Oscillator Dual Voltage-Controlled Multivibrator Low Power Voltage Controlled Oscillator
D,SD
Motorola Master Selection Guide
3.1-29
Logic: Standard, Special and Programmable
Selection by Function
Description
OSCILLATORS
Tech. ECL CMOS CMOS CMOS CMOS ECL ECL ECL CMOS ECL CMOS TTL TTL ECL CMOS ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL MC1648 MC14521B MC14541B MC14536B MC14415 MC10H160 MC10160 MC10E160 MC14531B MC10170
Device(s) - - - - - - - MC100E160 - - - SN74LS280 - MC100E193 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Pins 14 16 14 16 16 16 16 28 16 16 14 14 14 28 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
DIP P,L P,L P,L P,L P,L P,L P,L P P,L N N,J N
SM D,FN D D DW DW FN FN FN D FN D D D FN
Voltage Controlled Oscillator
OSCILLATOR/TIMERS
24-Stage Frequency Divider Programmable Oscillator Timer Programmable Timer Quad Precision Timer/Driver
PARITY CHECKERS
12-Bit Parity Generator/Checker 12-Bit Parity Generator/Checker, Register-Shiftable, Diff Output 12-Bit Parity Tree 9 + 2-Bit Parity Generator-Checker 9-Bit Odd/Even Parity Generator/Checker 9-Bit Parity Generator/Checker Error Detection and Correction Circuit
PHASE-LOCKED LOOP
MC74HC280 SN54LS280 MC74F280 MC10E193 MC14046B MC12080 MC12058 MC12038A MC12026A MC12026B MC12083 MC12093 MC12074 MC12028A MC12028B MC12073 MC12022A MC12022B MC12022SLA MC12022SLB MC12022TSA MC12022TSB MC12036A MC12036B MC12022LVA MC12022LVB MC12022TVA MC12022TVB MC12052A MC12053A MC12075 MC12066
Phase-Locked Loop
PRESCALERS
P,L P P P P P P P P P P P P P P P P P P P P P P
DW D D,SD D D D D D,SD D D D D D D D D D D D D D D D D D,SD D,SD
1.1GHz /10/20/40/80 Prescaler 1.1GHz /126/128, /254/256 Low Power Dual Modulus Prescaler 1.1GHz /127/128, /255/256 Low Power Dual Modulus Prescaler 1.1GHz /8/9, /16/17 Dual Modulus Prescaler 1.1GHz /2 Low Power Prescaler With Stand-By Mode 1.1GHz /2/4/8 Low Power Prescaler With Stand-By Mode 1.1GHz /256 Prescaler 1.1GHz /32/33, /64/65 Dual Modulus Prescaler 1.1GHz /32/33, /64/65 Dual Modulus Prescaler 1.1GHz /64 Prescaler 1.1GHz /64/65, /128/129 Dual Modulus Prescaler
1.1GHz /64/65, /128/129 Dual Modulus Prescaler With Stand-By y Mode 1.1GHz /64/65, /128/129 Low Voltage Dual Modulus Prescaler
ECL ECL ECL ECL ECL ECL
1.1GHz /64/65, /128/129 Super Low Power Dual Modulus Prescaler 1.1GHz /64/65, /128/129 Super Low Power Dual Modulus Prescaler With Stand-By Mode 1.3GHz /64 Prescaler 1.3GHz /64/256 Prescaler
ECL ECL ECL ECL
P
D D
Logic: Standard, Special and Programmable
3.1-30
Motorola Master Selection Guide
Selection by Function
Description
PRESCALERS
Tech. ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL MC12076 MC12078 MC12034A MC12034B MC12033A MC12033B MC12032A MC12032B MC12031A MC12031B MC12054A MC12095 MC12098 MC12079 MC12089 MC12019 MC12015 MC12016 MC12023 MC12017 MC12009 MC12018 MC12025 MC12013 MC12011 MC12090 MC10E196 MC10E195 MCM10146 MCM10152 MC10EL16
Device(s) - - - - - - - - - - - - - - - - - - - - - - - - - - MC100E196 MC100E195 - - MC100EL16 - - MC100EL17 - - - - MC100E116 MC100E416
Pins 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 8 8 16 16 16 28 28 16 16 8 8 16 20 16 16 16 16 28 28
DIP P P P P P P P P P P
SM D D D D D D D D D D D,SD D,SD D
1.3GHz /256 Prescaler 2.0GHz /32/33, /64/65 Dual Modulus Prescaler 2.0GHz /32/33, /64/65 Low Voltage Dual Modulus Prescaler 2.0GHz /64/65, /128/129 Dual Modulus Prescaler 2.0GHz /64/65, /128/129 Low Voltage Dual Modulus Prescaler 2.0GHz /64/65, /128/129 Super Low Power Dual Modulus Prescaler 2.5GHz /2, /4 Low Power Prescaler With Satnd-By Mode 2.5GHz /8192 Prescaler 2.8GHz /64/128/256 Prescaler 225MHz /20/21 Dual Modulus Prescaler 225MHz /32/33 Dual Modulus Prescaler 225MHz /40/41 Dual Modulus Prescaler 225MHz /64 Prescaler 225MHz /64/65 Dual Modulus Prescaler 480MHz /5/6 Dual Modulus Prescaler 520MHz /128/129 Dual Modulus Prescaler 520MHz /64/65 Dual Modulus Prescaler 550MHz /10/11 Dual Modulus Prescaler 550MHz /8/9 Dual Modulus Prescaler 750MHz /2 UHF Prescaler
PROGRAMMABLE DELAY CHIPS
P P P,L P,L P,L P P,L P,L P,L P P,L P,L P,L
D D D D D D D D D
Programmable Delay Chip (Dig 80ps Anal. 1.6 Ps/mv) Programmable Delay Chip (Digitally Selectable 20ps Res)
RAMs
FN FN L L D D P,L L P,L P,L L FN FN FN FN FN DW
1024 X 1-Bit Random Access Memory 256 X 1-Bit Random Access Memory
RECEIVERS
Differential Receiver High Speed Triple Line Receiver Low-Voltage Quad Differential Line Receiver Quad Bus Receiver Quad Line Receiver
MC100LVEL16 MC10216 MC100LVEL17 MC10129 MC10H115 MC10115 MC1692 MC10E116 MC10E416
Quint Differential Line Receiver
ECL ECL
Motorola Master Selection Guide
3.1-31
Logic: Standard, Special and Programmable
Selection by Function
Description
RECEIVERS
Tech. ECL ECL ECL MC10H116 MC10114 MC10116 MC14580B MC74F378 MC10H145 SN54LS170 SN54LS670 MCM10145 MCM10143 MC74F13 SN54LS13 MC14583B MC74AC14
Device(s) - - - - - - SN74LS170 SN74LS670 - - - SN74LS13 - - - - SN74LS14 - - MC74HC14A - MC74HCT14A MC74HC132A - - - - SN74LS132 - - - - - - - - - - - MC100E212
Pins 16 16 16 24 16 16 16 16 16 24 14 14 16 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 16,20 20 24,32 28 28 16 8,20 8,20 16 14 14 28
DIP P,L P,L P,L P,L N P,L N,J N,J L L N N,J P N N N N,J P,L P,L N,J
SM D,FN FN FN D D FN D D
Triple Line Receiver
REGISTERS
4 X 4 Multiport Register Hex Parallel D Register With Enable
REGISTER FILES
CMOS TTL ECL TTL TTL ECL ECL TTL TTL CMOS CMOS CMOS TTL TTL
16 X 4-Bit Register File (RAM) 4 X 4 Register File Open Collector 4 X 4 Register File With 3-State Outputs 64-Bit Register File (RAM) 8 X 2 Multiport Register File (RAM)
SCHMITT TRIGGERS
Dual 4-Input NAND Schmitt Trigger Dual Schmitt Trigger Hex Inverter Schmitt Trigger
D D D D D D D D D D,DT D, DT,M
MC74ACT14 MC74F14 SN54LS14 MC14106B MC14584B MC54HC14A MC74VHC14 MC54HCT14A MC54HC132A MC74AC132 MC74ACT132 MC74F132 MC14093B SN54LS132 MCCS142237 MCCS142233 MCCS142235 MCCS142236 MCCS142238 MCCS142239 MPA1765 MPA17128 MC14557B MC14562B MC14006B MC10E212
Hex Schmitt Trigger Hex Schmitt Trigger Inverter
CMOS CMOS CMOS CMOS CMOS
N,J N,J N N N P,L N,J
D D D D D D D DW, DT FN DW, *FA DW DW D,DW
Quad 2-Input NAND Gate With Schmitt Trigger Inputs Quad 2-Input NAND Schmitt Trigger
CMOS CMOS CMOS TTL CMOS
Quad 2-Input Schmitt Trigger NAND Gate
SCSI BUS TERMINATORS
TTL CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS ECL
9-Bit Switchable Active SCSI-2 Bus Term (110) with Volt Reg 9-Bit Switchable SCSI Bus Term (220 & 330: Passive) 18-Bit Active SCSI Bus Terminator (*Also Available in 32-Pin QFP Package) 18-Bit Switchable Active SCSI-2 Bus Term (110) with Volt Reg 18-Bit Switchable Active SCSI-2 Bus Term (110) with Volt Reg Plus Inverted Disconnect 9-Bit Switchable Active SCSI Bus Terminator (110) with Volt Reg
SERIAL EPROMs
Serial EPROM for MPA1016: 8-Pin DIP and SOIC; 20-Pin PLCC Serial EPROM for MPA1036: 8-Pin DIP and SOIC; 20-Pin PLCC
SHIFT REGISTERS
N P P,L P,L P,L
D,FN D,FN DW D FN
1-to-64-Bit Variable Length Shift Register 128-Bit Static Shift Register 18-Bit Static Shift Register 3-Bit Scannable Registered Address Driver, ECL
Logic: Standard, Special and Programmable
3.1-32
Motorola Master Selection Guide
Selection by Function
Description
SHIFT REGISTERS
Tech. CMOS CMOS TTL CMOS TTL MC74AC194
Device(s) - - - - SN74LS194A - SN74LS95B - - - - - - - - - - SN74LS165 MC100E241 - MC74HC165 MC74HC589 MC74HC589A MC74HC597 MC74HC597A SN74LS164 MC74HC164 MC74HC164A MC74HC595A - MC100E141 SN74LS166 SN74LS322A SN74LS299 SN74LS323 - - - - - - - - - MC100E142 -
Pins 16 16 16 16 16 16 14 16 16 16 16 16 16 16 16 16 20 16 28 14 16 16 16 16 16 14 14 14 16 16 28 16 20 20 20 16 16 20 20 20 20 20 20 16 28 16
DIP N N N N N,J N N,J P,L N,J N N N N P,L P,L P,L N N,J N N,J N,J N,J N,J N,J N,J N,J N,J N,J
SM D D D D D D D D D D D FN FN D DW D FN D D D D,SD DT D D,DT D D D,DT D,DT D, DT,M FN
4-Bit Bidirectional Universal Shift Register
MC74ACT194 MC74F194 MC74HC194 SN54LS194A MC74F195 SN54LS95B MC14035B SN74LS395 MC74AC350 MC74ACT350 MC74F350 MC74HC195 MC10H141 MC10141 MC14194B MC74HC299 SN54LS165 MC10E241 MC74F164 MC54HC165 MC54HC589 MC54HC589A MC54HC597 MC54HC597A SN54LS164 MC54HC164 MC54HC164A MC54HC595A MC74VHC595 MC10E141 SN54LS166 SN54LS322A SN54LS299 SN54LS323 MC14014B MC14021B MC74F323 MC74AC299 MC74ACT299 MC74AC323 MC74ACT323 MC74F299 MC14094B MC10E142 MC14015B
4-Bit Shift Register
TTL TTL CMOS
4-Bit Shift Register With 3-State Outputs 4-Bit Shifter With 3-State 4-Bit Shifter, With 3-State Outputs 4-Bit Universal Shift Register
TTL CMOS CMOS TTL CMOS ECL ECL CMOS
8-Bit Bidirectional Universal Shift Register With parallel I/O 8-Bit Parallel-to-Serial Shift Register 8-Bit Scannable Register 8-Bit Serial In-Serial Out Shift Register 8-Bit Serial or Parallel-Input/Serial-Output Shift Register 8-Bit Serial or Parallel-Input/Serial-Output Shift Register p p g With 3 State O tp ts 3-State Outputs 8-Bit Serial or Parallel-Input/Serial-Output Shift Register With p p g Input Inp t Latch 8-Bit Serial-In/Parallel-Out Shift Register 8-Bit Serial-Input/Parallel-Output Shift Register 8-Bit Serial-Input/Serial or Parallel-Output Shift Register With Latched 3-State Outputs
CMOS TTL ECL TTL CMOS CMOS CMOS CMOS CMOS TTL CMOS CMOS CMOS CMOS
8-Bit Shift Register 8-Bit Shift Registers With Sign Extend 8-Bit Shift/Storage Register With 3-State Outputs 8-Bit Static Shift Register 8-Input Shift/Storage Register W/Synchronous Reset and Common I/O Pins 8-Input Universal Shift/Storage Register With Common Parallel I/O p g g Pins: Pins With 3 State O tp ts 3-State Outputs 8-Input Universal Shift/Storage Register With Syn Reset/Common p g g y Parallel I/O Pins With 3 State O tp ts Pins: 3-State Outputs 8-Input Universal Shift/Storage Register, W/Common Parallel I/O Pins 8-Stage Shift/Store Register With 3-State Outputs 9-Bit Shift Register, 700MHz, With Asynchronous Master Reset Dual 5-Bit Shift Register
ECL TTL TTL TTL TTL CMOS CMOS TTL CMOS CMOS CMOS CMOS TTL CMOS ECL CMOS
N,J N,J N,J N,J P,L P,L N N N N N N P,L P,L
D DW DW DW D D DW DW DW DW DW DW D FN D
Motorola Master Selection Guide
3.1-33
Logic: Standard, Special and Programmable
Selection by Function
Description
SHIFT REGISTERS
Tech. CMOS CMOS CMOS TTL ECL ECL ECL ECL ECL ECL ECL CMOS ECL ECL ECL CMOS CMOS CMOS CMOS MC14517B MC14549B MC14559B
Device(s) - - - SN74LS195A - - - - - - MC100H680 - - - MC100H681 - - - - - - - - - - - SN74LS642 SN74LS641 -
Pins 16 16 16 16 16,20 16 16,20 16,20 8 20 28 24 16 20 28 56 48 56 56 24 20 20 24 24 24 24 20 20 20
DIP P P,L P,L N,J
SM DW DW DW D D,M, DT DT D,DT D,DT D
DW,SD
Dual 64-Bit Static Shift Register Successive Approximation Register Universal 4-Bit Shift Register
SYNTHESIZERS
SN54LS195A MC12202 MC12181 MC12206 MC12210 MC12179 MC74F2245 MC10H680 MC74LVX4245 MC10804 MC10805 MC10H681
MC74LCX16543A MC74LCX16245 MC74LCX16500 MC74LCX16501
1.1GHz Serial Input Synthesizer With /64/65, /128/129 Prescaler 125-1000MHz Frequency Synthesizer With Parallel Programming Interface 2.0GHz Serial Input Synthesizer With /64/65, /128/129 Prescaler 2.5GHz Serial Input Synthesizer With /32/33, /64/65 Prescaler 2.7GHz Frequency Synthesizer
TRANSCEIVERS
25 Octal Bidirectional Transceiver w/ 3-State Inputs and Outputs 4-Bit Differential ECL Bus/TTL Bus Transceiver Dual Supply Octal Translating Transceiver ECL/TTL Inverting Bidirectional Transceivers With Latch (4-Bit) ECL/TTL Inverting Bidirectional Transceivers With Latch (5-Bit) Hex ECL/TTL Transceiver With Latches Low-Voltage CMOS 16-Bit Latching Transceiver, 3-State, Non-Inverting With 5V Tolerant Inputs and Outputs Low-Voltage CMOS 16-Bit Transceiver, 3-State, Non-Inverting With 5V Tolerant Inputs and Outputs Low-Voltage CMOS 18-Bit Universal Bus Transceiver, 3-State, Non-Inverting With 5V Tolerant Inputs and Outputs Low-Voltage CMOS Octal Registered Transceiver With Dual Output and Clock Enables, With 5V Tolerant Inputs and Outputs Low-Voltage CMOS Octal Transceiver, 3-State, Non-Inverting With 5V Tolerant Inputs and Outputs Low-Voltage Quiet CMOS Octal Transceiver, 3-State, Non-Inverting Low-Voltage CMOS Octal Transceiver/Registered Transceiver With 5V Tolerant Inputs and Outputs Low-Voltage CMOS Octal Transceiver/Registered Transceiver With Dual Enable, With 5V Tolerant Inputs and Outputs Low-Voltage Quiet CMOS Octal Transceiver/Registered Transceiver Low-Voltage Quiet CMOS Octal Transceiver/Registered Transceiver Octal Bus Transceiver/Inverting With Open Collector Octal Bus Transceiver/Non-Inverting With Open Collector Quad Futurebus Backplane Transceiver, With 3-State Outputs and Open Collector
TRANSLATORS
FN
DW,DT
L L FN DT DT DT DT DW, SD,DT M,DW, DT M,DW, SD,DT DW, SD,DT DW, DT DW, SD,DT DW, SD,DT N,J N,J DW DW FN
CMOS CMOS CMOS CMOS CMOS CMOS CMOS TTL TTL TTL
MC74LCX2952 MC74LCX245 MC74LVQ245 MC74LCX646 MC74LCX652 MC74LVQ646 MC74LVQ652 SN54LS642 SN54LS641 MC74F3893A
9-Bit ECL/TTL Translator 9-Bit Latch ECL/TTL Translator 9-Bit Latch TTL/ECL Translator 9-Bit TTL/ECL Translator Differential ECL/TTL Translator Differential PECL/TTL Translator Dual Differential PECL/TTL Translator Dual LVTTL/LVCMOS to Differential PECL Translator Dual TTL/Differential PECL Translator
ECL ECL ECL ECL ECL ECL ECL ECL ECL
MC10H601 MC10H603 MC10H602 MC10H600 MC10ELT25 MC10ELT21 MC100ELT23 MC100LVELT22 MC10ELT22
MC100H601 MC100H603 MC100H602 MC100H600 MC100ELT25 MC100ELT21 - - MC100ELT22
28 28 28 28 8 8 8 8 8
FN FN FN FN D D D D D
Logic: Standard, Special and Programmable
3.1-34
Motorola Master Selection Guide
Selection by Function
Description
TRANSLATORS
Tech. ECL ECL CMOS ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL CMOS CMOS CMOS MC10H350 MC10191 MC14504B MC10H352 MC10H125 MC10125 MC10190 MC10H424 MC10124 MC10H124 MC10H351 MC10H605 MC10H607 MC10H604 MC10H606 MC10177
Device(s) - - - - - - - - - - - MC100H605 MC100H607 MC100H604 MC100H606 - MC100EL90 - - MC100ELT24 MC100ELT20 MC100ELT28 - - -
Pins 16 16 16 20 16 16 16 16 16 16 20 28 28 28 28 16 20 20 20 8 8 8 16 8 8
DIP P,L P,L P,L P,L P,L P,L P P,L P,L P,L P,L
SM FN D FN FN FN FN FN FN FN FN FN FN FN
ECL/TTL Translator (Single P.S. @+ 5.0V) Hex ECL/MST Translator Hex TTL OR CMOS/CMOS Hex Level Shifter Quad CMOS/ECL Translator (Single P.S. @+ 5.0V) Quad MECL/TTL Translator Quad MST/ECL Translator Quad TTL/ECL Translator (ECL Strobe) Quad TTL/MECL Translator Quad TTL/MECL Translator, With TTL Strobe Input Quad TTL/NMOS-to-PECL Translator (Single P.S. @+ 5.0V) Registered Hex ECL/TTL Translator Registered Hex PECL/TTL Translator Registered Hex TTL/ECL Translator Registered Hex TTL/PECL Translator Triple MECL/NMOS Translator Triple ECL to PECL Translator Triple PECL to LVPECL Translator Triple PECL to ECL Translator TTL/Differential ECL Translator TTL/Differential PECL Translator TTL to Differential PECL/Differential PECL to TTL Translator
VCO
L DW DW DW D D D N D D,SD D,SD
MC100LVEL90 MC100LVEL92 MC100LVEL91 MC10ELT24 MC10ELT20 MC10ELT28 MC74HC4046A MC12147 MC12149
Phase-Locked-Loop With VCO Low Power Voltage Controlled Oscillator Buffer Low Power Voltage Controlled Oscillator Buffer
Motorola Master Selection Guide
3.1-35
Logic: Standard, Special and Programmable
Device Index
MC100E016 MC100E101 MC100E104 MC100E107 MC100E111 MC100E112 MC100E116 MC100E122 MC100E131 MC100E136 MC100E137 MC100E141 MC100E142 MC100E143 MC100E150 MC100E151 MC100E154 MC100E155 MC100E156 MC100E157 MC100E158 MC100E160 MC100E163 MC100E164 MC100E166 MC100E167 MC100E171 MC100E175 MC100E193 MC100E195 MC100E196 MC100E210 MC100E211 MC100E212 MC100E241 MC100E256 MC100E310 MC100E336 MC100E337 MC100E404 MC100E416 MC100E431 MC100E445 MC100E446 MC100E451 MC100E452 MC100E457 MC100EL01 MC100EL04 MC100EL05 MC100EL07 3.1-15 3.1-23 3.1-23 3.1-23 3.1-12 3.1-25 3.1-31 3.1-25 3.1-18 3.1-14 3.1-15 3.1-33 3.1-33 3.1-18 3.1-26 3.1-18 3.1-26 3.1-26 3.1-26 3.1-29 3.1-27 3.1-30 3.1-27 3.1-27 3.1-14 3.1-18 3.1-27 3.1-26 3.1-30 3.1-31 3.1-31 3.1-9 3.1-12 3.1-32 3.1-33 3.1-26 3.1-9 3.1-10 3.1-10 3.1-23 3.1-31 3.1-18 3.1-14 3.1-14 3.1-18 3.1-18 3.1-29 3.1-22 3.1-22 3.1-22 3.1-22 MC100EL11 MC100EL12 MC100EL13 MC100EL14 MC100EL15 MC100EL16 MC100EL17 MC100EL29 MC100EL30 MC100EL31 MC100EL32 MC100EL33 MC100EL34 MC100EL35 MC100EL38 MC100EL39 MC100EL51 MC100EL52 MC100EL56 MC100EL57 MC100EL58 MC100EL59 MC100EL90 MC100ELT20 MC100ELT21 MC100ELT22 MC100ELT23 MC100ELT24 MC100ELT25 MC100ELT28 MC100H600 MC100H601 MC100H602 MC100H603 MC100H604 MC100H605 MC100H606 MC100H607 MC100H640 MC100H641 MC100H642 MC100H643 MC100H644 MC100H646 MC100H660 MC100H680 MC100H681 MC100LVE111 MC100LVE164 MC100LVE210 MC100LVE222 3.1-12 3.1-25 3.1-9 3.1-12 3.1-12 3.1-31 3.1-31 3.1-19 3.1-21 3.1-18 3.1-17 3.1-17 3.1-13 3.1-19 3.1-13 3.1-13 3.1-18 3.1-18 3.1-28 3.1-27 3.1-27 3.1-29 3.1-35 3.1-35 3.1-34 3.1-34 3.1-34 3.1-35 3.1-34 3.1-35 3.1-34 3.1-34 3.1-34 3.1-34 3.1-35 3.1-35 3.1-35 3.1-35 3.1-13 3.1-13 3.1-13 3.1-13 3.1-13 3.1-13 3.1-27 3.1-34 3.1-34 3.1-12 3.1-28 3.1-9 3.1-13 MC100LVE310 MC100LVEL01 MC100LVEL05 MC100LVEL11 MC100LVEL12 MC100LVEL13 MC100LVEL14 MC100LVEL16 MC100LVEL17 MC100LVEL29 MC100LVEL30 MC100LVEL31 MC100LVEL32 MC100LVEL33 MC100LVEL38 MC100LVEL39 MC100LVEL51 MC100LVEL56 MC100LVEL59 MC100LVEL90 MC100LVEL91 MC100LVEL92 MC100LVELT22 MC100SX1230 MC10101 MC10102 MC10103 MC10104 MC10105 MC10106 MC10107 MC10109 MC10110 MC10111 MC10113 MC10114 MC10115 MC10116 MC10117 MC10121 MC10123 MC10124 MC10125 MC10129 MC10130 MC10131 MC10133 MC10134 MC10135 MC10136 MC10137 3.1-9 3.1-22 3.1-22 3.1-9 3.1-25 3.1-9 3.1-12 3.1-31 3.1-31 3.1-19 3.1-21 3.1-20 3.1-17 3.1-17 3.1-13 3.1-13 3.1-18 3.1-28 3.1-29 3.1-35 3.1-35 3.1-35 3.1-34 3.1-18 3.1-23 3.1-24 3.1-24 3.1-21 3.1-23 3.1-24 3.1-23 3.1-23 3.1-24 3.1-24 3.1-23 3.1-32 3.1-31 3.1-32 3.1-23 3.1-22 3.1-12 3.1-35 3.1-35 3.1-31 3.1-26 3.1-19 3.1-27 3.1-28 3.1-19 3.1-16 3.1-16
TTL, ECL, CMOS and Special Logic Circuits
3.1-36
Motorola Master Selection Guide
Device Index
MC10138 MC10141 MC10153 MC10154 MC10158 MC10159 MC10160 MC10161 MC10162 MC10163 MC10164 MC10165 MC10166 MC10170 MC10171 MC10172 MC10173 MC10174 MC10175 MC10176 MC10177 MC10178 MC10180 MC10181 MC10186 MC10188 MC10189 MC10190 MC10191 MC10192 MC10193 MC10195 MC10197 MC10198 MC10210 MC10211 MC10212 MC10216 MC10231 MC10804 MC10805 MC10E016 MC10E101 MC10E104 MC10E107 MC10E111 MC10E112 MC10E116 MC10E122 MC10E131 MC10E136 MC10E137 3.1-15 3.1-33 3.1-27 3.1-15 3.1-28 3.1-28 3.1-30 3.1-16 3.1-16 3.1-17 3.1-27 3.1-18 3.1-14 3.1-30 3.1-16 3.1-17 3.1-29 3.1-28 3.1-27 3.1-19 3.1-35 3.1-15 3.1-9 3.1-9 3.1-19 3.1-25 3.1-25 3.1-35 3.1-35 3.1-12 3.1-17 3.1-25 3.1-21 3.1-29 3.1-24 3.1-24 3.1-23 3.1-31 3.1-19 3.1-34 3.1-34 3.1-15 3.1-23 3.1-23 3.1-23 3.1-12 3.1-25 3.1-31 3.1-25 3.1-18 3.1-14 3.1-15 MC10E141 MC10E142 MC10E143 MC10E150 MC10E151 MC10E154 MC10E155 MC10E156 MC10E157 MC10E158 MC10E160 MC10E163 MC10E164 MC10E1651 MC10E1652 MC10E166 MC10E167 MC10E171 MC10E175 MC10E193 MC10E195 MC10E196 MC10E197 MC10E211 MC10E212 MC10E241 MC10E256 MC10E336 MC10E337 MC10E404 MC10E411 MC10E416 MC10E431 MC10E445 MC10E446 MC10E451 MC10E452 MC10E457 MC10EL01 MC10EL04 MC10EL05 MC10EL07 MC10EL11 MC10EL12 MC10EL15 MC10EL16 MC10EL31 MC10EL32 MC10EL33 MC10EL34 MC10EL35 MC10EL51 3.1-33 3.1-33 3.1-18 3.1-26 3.1-18 3.1-26 3.1-26 3.1-26 3.1-29 3.1-27 3.1-30 3.1-27 3.1-27 3.1-14 3.1-14 3.1-14 3.1-18 3.1-27 3.1-26 3.1-30 3.1-31 3.1-31 3.1-27 3.1-12 3.1-32 3.1-33 3.1-26 3.1-10 3.1-10 3.1-23 3.1-13 3.1-31 3.1-18 3.1-14 3.1-14 3.1-18 3.1-18 3.1-29 3.1-22 3.1-22 3.1-22 3.1-22 3.1-12 3.1-25 3.1-12 3.1-31 3.1-18 3.1-17 3.1-17 3.1-13 3.1-19 3.1-18 MC10EL52 MC10EL57 MC10EL58 MC10EL89 MC10ELT20 MC10ELT21 MC10ELT22 MC10ELT24 MC10ELT25 MC10ELT28 MC10H100 MC10H101 MC10H102 MC10H103 MC10H104 MC10H105 MC10H106 MC10H107 MC10H109 MC10H113 MC10H115 MC10H116 MC10H117 MC10H118 MC10H119 MC10H121 MC10H123 MC10H124 MC10H125 MC10H130 MC10H131 MC10H135 MC10H136 MC10H141 MC10H145 MC10H158 MC10H159 MC10H16 MC10H160 MC10H161 MC10H162 MC10H164 MC10H165 MC10H166 MC10H171 MC10H172 MC10H173 MC10H174 MC10H175 MC10H176 MC10H179 MC10H180 3.1-18 3.1-27 3.1-27 3.1-17 3.1-35 3.1-34 3.1-34 3.1-35 3.1-34 3.1-35 3.1-24 3.1-23 3.1-24 3.1-24 3.1-21 3.1-23 3.1-24 3.1-23 3.1-23 3.1-23 3.1-31 3.1-32 3.1-23 3.1-23 3.1-22 3.1-22 3.1-12 3.1-35 3.1-35 3.1-26 3.1-19 3.1-19 3.1-16 3.1-33 3.1-32 3.1-29 3.1-29 3.1-14 3.1-30 3.1-16 3.1-16 3.1-27 3.1-18 3.1-14 3.1-17 3.1-17 3.1-28 3.1-28 3.1-27 3.1-19 3.1-9 3.1-9
Motorola Master Selection Guide
3.1-37
TTL, ECL, CMOS and Special Logic Circuits
Device Index
MC10H181 MC10H186 MC10H188 MC10H189 MC10H209 MC10H210 MC10H211 MC10H330 MC10H332 MC10H334 MC10H350 MC10H351 MC10H352 MC10H423 MC10H424 MC10H600 MC10H601 MC10H602 MC10H603 MC10H604 MC10H605 MC10H606 MC10H607 MC10H640 MC10H641 MC10H642 MC10H643 MC10H644 MC10H645 MC10H646 MC10H660 MC10H680 MC10H681 MC10SX1125 MC10SX1130 MC10SX1189 MC12002 MC12009 MC12011 MC12013 MC12014 MC12015 MC12016 MC12017 MC12018 MC12019 MC12022A MC12022B MC12022LVA MC12022LVB MC12022SLA MC12022SLB 3.1-9 3.1-19 3.1-25 3.1-25 3.1-23 3.1-24 3.1-24 3.1-12 3.1-10 3.1-12 3.1-35 3.1-35 3.1-35 3.1-12 3.1-35 3.1-34 3.1-34 3.1-34 3.1-34 3.1-35 3.1-35 3.1-35 3.1-35 3.1-13 3.1-13 3.1-13 3.1-13 3.1-13 3.1-13 3.1-13 3.1-27 3.1-34 3.1-34 3.1-9 3.1-13, 3.1-17 3.1-13 3.1-17 3.1-31 3.1-31 3.1-31 3.1-15 3.1-31 3.1-31 3.1-31 3.1-31 3.1-31 3.1-30 3.1-30 3.1-30 3.1-30 3.1-30 3.1-30 MC12022TSA MC12022TSB MC12022TVA MC12022TVB MC12023 MC12025 MC12026A MC12026B MC12028A MC12028B MC12031A MC12031B MC12032A MC12032B MC12033A MC12033B MC12034A MC12034B MC12036A MC12036B MC12038A MC12040 MC12052A MC12053A MC12054A MC12058 MC12061 MC12066 MC12073 MC12074 MC12075 MC12076 MC12078 MC12079 MC12080 MC12083 MC12089 MC12090 MC12093 MC12095 MC12098 MC12100 MC12101 MC12147 MC12148 MC12149 MC12179 MC12181 MC12202 MC12206 MC12210 MC12429 3.1-30 3.1-30 3.1-30 3.1-30 3.1-31 3.1-31 3.1-30 3.1-30 3.1-30 3.1-30 3.1-31 3.1-31 3.1-31 3.1-31 3.1-31 3.1-31 3.1-31 3.1-31 3.1-30 3.1-30 3.1-30 3.1-17 3.1-30 3.1-30 3.1-31 3.1-30 3.1-29 3.1-30 3.1-30 3.1-30 3.1-30 3.1-31 3.1-31 3.1-31 3.1-30 3.1-30 3.1-31 3.1-31 3.1-30 3.1-31 3.1-31 3.1-29 3.1-29 3.1-35 3.1-29 3.1-35 3.1-34 3.1-34 3.1-34 3.1-34 3.1-34 3.1-13 MC12430 MC12439 MC14001B MC14001UB MC14002B MC14002UB MC14006B MC14007UB MC14008B MC14011B MC14011UB MC14012B MC14012UB MC14013B MC14014B MC14015B MC14016B MC14017B MC14018B MC14020B MC14021B MC14022B MC14023B MC14023UB MC14024B MC14025B MC14025UB MC14027B MC14028B MC14029B MC14035B MC14038B MC14040B MC14042B MC14043B MC14044B MC14046B MC14049B MC14049UB MC14050B MC14051B MC14052B MC14053B MC14060B MC14066B MC14067B MC14068B MC14069UB MC14070B MC14071B MC14072B MC14073B 3.1-13 3.1-13 3.1-24 3.1-24 3.1-24 3.1-24 3.1-32 3.1-25 3.1-9 3.1-22 3.1-22 3.1-21 3.1-21 3.1-18 3.1-33 3.1-33 3.1-29 3.1-15 3.1-15 3.1-14 3.1-33 3.1-15 3.1-22 3.1-22 3.1-14 3.1-24 3.1-24 3.1-19 3.1-16 3.1-15 3.1-33 3.1-9 3.1-14 3.1-27 3.1-27 3.1-27 3.1-30 3.1-25 3.1-25 3.1-25 3.1-27 3.1-28 3.1-29 3.1-14 3.1-29 3.1-27 3.1-21 3.1-25 3.1-23 3.1-24 3.1-24 3.1-22
TTL, ECL, CMOS and Special Logic Circuits
3.1-38
Motorola Master Selection Guide
Device Index
MC14075B MC14076B MC14077B MC14078B MC14081B MC14082B MC14093B MC14094B MC14099B MC14106B MC14161B MC14163B MC14174B MC14175B MC14194B MC14415 MC14490 MC14500B MC14501UB MC14502B MC14503B MC14504B MC14506UB MC14508B MC14510B MC14511B MC14512B MC14513B MC14514B MC14515B MC14516B MC14517B MC14518B MC14519B MC14520B MC14521B MC14522B MC14526B MC14527B MC14528B MC14529B MC14530B MC14531B MC14532B MC14534B MC14536B MC14538B MC14539B MC14541B MC14543B MC14544B MC14547B 3.1-25 3.1-21 3.1-23 3.1-24 3.1-21 3.1-21 3.1-32 3.1-33 3.1-26 3.1-32 3.1-14 3.1-14 3.1-19 3.1-21 3.1-33 3.1-30 3.1-9 3.1-25 3.1-23 3.1-25 3.1-10 3.1-35 3.1-23 3.1-26 3.1-15 3.1-17 3.1-27 3.1-17 3.1-16 3.1-16 3.1-15 3.1-34 3.1-15 3.1-22 3.1-15 3.1-30 3.1-15 3.1-15 3.1-9 3.1-29 3.1-28 3.1-23 3.1-30 3.1-17 3.1-14 3.1-30 3.1-29 3.1-28 3.1-30 3.1-17 3.1-17 3.1-17 MC14549B MC14551B MC14553B MC14555B MC14556B MC14557B MC14558B MC14559B MC14560B MC14561B MC14562B MC14566B MC14568B MC14569B MC14572UB MC14580B MC14583B MC14584B MC14585B MC14598B MC14599B MC1648 MC1650 MC1651 MC1658 MC1660 MC1662 MC1670 MC1672 MC1692 MC4016 MC4018 MC4024 MC4044 MC4316 MC4324 MC4344 MC54HC00A MC54HC02A MC54HC04A MC54HC08A MC54HC132A MC54HC138A MC54HC139A MC54HC14A MC54HC154 MC54HC157A MC54HC158 MC54HC160 MC54HC161A MC54HC162 MC54HC163A 3.1-34 3.1-28 3.1-14 3.1-17 3.1-17 3.1-32 3.1-17 3.1-34 3.1-9 3.1-9 3.1-32 3.1-15 3.1-15 3.1-15 3.1-23 3.1-32 3.1-32 3.1-32 3.1-14 3.1-26 3.1-26 3.1-30 3.1-14 3.1-14 3.1-29 3.1-23 3.1-24 3.1-20 3.1-23 3.1-31 3.1-16 3.1-16 3.1-29 3.1-17 3.1-16 3.1-29 3.1-17 3.1-22 3.1-24 3.1-25 3.1-21 3.1-32 3.1-16 3.1-17 3.1-32 3.1-16 3.1-28 3.1-28 3.1-15 3.1-15 3.1-15 3.1-15 MC54HC164 MC54HC164A MC54HC165 MC54HC174A MC54HC175 MC54HC175A MC54HC240A MC54HC241A MC54HC244A MC54HC245A MC54HC251 MC54HC259 MC54HC27 MC54HC273A MC54HC32A MC54HC354 MC54HC365 MC54HC366 MC54HC367 MC54HC373A MC54HC374A MC54HC390 MC54HC393 MC54HC4016 MC54HC4040A MC54HC4049 MC54HC4050 MC54HC4051 MC54HC4053 MC54HC4060 MC54HC4060A MC54HC4066 MC54HC4351 MC54HC4353 MC54HC4538A MC54HC533A MC54HC534A MC54HC540A MC54HC541A MC54HC563A MC54HC573A MC54HC574A MC54HC589 MC54HC589A MC54HC595A MC54HC597 MC54HC597A MC54HC640A MC54HC646 MC54HC688 MC54HC74A MC54HC86 3.1-33 3.1-33 3.1-33 3.1-19 3.1-21 3.1-21 3.1-11 3.1-11 3.1-12 3.1-12 3.1-27 3.1-16 3.1-24 3.1-20 3.1-24 3.1-27 3.1-10 3.1-10 3.1-10 3.1-27 3.1-20 3.1-15 3.1-15 3.1-29 3.1-14 3.1-25 3.1-25 3.1-27 3.1-29 3.1-14 3.1-14 3.1-29 3.1-27 3.1-29 3.1-29 3.1-27 3.1-20 3.1-11 3.1-11 3.1-27 3.1-27 3.1-20 3.1-33 3.1-33 3.1-33 3.1-33 3.1-33 3.1-11 3.1-12 3.1-14 3.1-19 3.1-23
Motorola Master Selection Guide
3.1-39
TTL, ECL, CMOS and Special Logic Circuits
Device Index
MC54HC86A MC54HCT00A MC54HCT08A MC54HCT14A MC54HCT161A MC54HCT163A MC54HCT241A MC54HCT244A MC54HCT245A MC54HCT32A MC54HCT373A MC54HCT374A MC54HCT574A MC660 MC661 MC662 MC663 MC664 MC667 MC668 MC669 MC670 MC671 MC672 MC677 MC678 MC68150*33 MC68150*40 MC68194 MC74AC00 MC74AC02 MC74AC04 MC74AC05 MC74AC08 MC74AC10 MC74AC109 MC74AC11 MC74AC112 MC74AC113 MC74AC125 MC74AC126 MC74AC132 MC74AC138 MC74AC139 MC74AC14 MC74AC151 MC74AC153 MC74AC157 MC74AC158 MC74AC160 MC74AC161 MC74AC162 3.1-23 3.1-22 3.1-21 3.1-32 3.1-15 3.1-15 3.1-11 3.1-11 3.1-10 3.1-24 3.1-26 3.1-20 3.1-20 3.1-18 3.1-18 3.1-18 3.1-19 3.1-20 3.1-29 3.1-25 3.1-18 3.1-25 3.1-25 3.1-25 3.1-25 3.1-25 3.1-10 3.1-10 3.1-12 3.1-22 3.1-24 3.1-25 3.1-25 3.1-21 3.1-22 3.1-19 3.1-22 3.1-19 3.1-19 3.1-12 3.1-12 3.1-32 3.1-16 3.1-17 3.1-32 3.1-27 3.1-28 3.1-29 3.1-29 3.1-16 3.1-16 3.1-16 MC74AC163 MC74AC174 MC74AC175 MC74AC190 MC74AC194 MC74AC20 MC74AC240 MC74AC241 MC74AC244 MC74AC245 MC74AC251 MC74AC253 MC74AC256 MC74AC257 MC74AC258 MC74AC259 MC74AC273 MC74AC299 MC74AC32 MC74AC323 MC74AC350 MC74AC352 MC74AC353 MC74AC373 MC74AC374 MC74AC377 MC74AC378 MC74AC4020 MC74AC4040 MC74AC533 MC74AC534 MC74AC540 MC74AC541 MC74AC563 MC74AC564 MC74AC573 MC74AC574 MC74AC620 MC74AC623 MC74AC640 MC74AC643 MC74AC646 MC74AC648 MC74AC652 MC74AC74 MC74AC810 MC74AC86 MC74ACT00 MC74ACT02 MC74ACT04 MC74ACT05 MC74ACT08 3.1-16 3.1-19 3.1-20 3.1-16 3.1-33 3.1-21 3.1-11 3.1-11 3.1-11 3.1-10 3.1-27 3.1-28 3.1-26 3.1-28 3.1-28 3.1-26 3.1-20 3.1-33 3.1-24 3.1-33 3.1-33 3.1-28 3.1-28 3.1-26 3.1-20 3.1-20 3.1-18 3.1-14 3.1-14 3.1-26 3.1-20 3.1-11 3.1-11 3.1-26 3.1-20 3.1-26 3.1-20 3.1-10 3.1-10 3.1-10 3.1-10 3.1-11 3.1-11 3.1-11 3.1-18 3.1-23 3.1-23 3.1-22 3.1-24 3.1-25 3.1-25 3.1-21 MC74ACT10 MC74ACT109 MC74ACT11 MC74ACT112 MC74ACT113 MC74ACT125 MC74ACT126 MC74ACT132 MC74ACT138 MC74ACT139 MC74ACT14 MC74ACT151 MC74ACT153 MC74ACT157 MC74ACT158 MC74ACT160 MC74ACT161 MC74ACT162 MC74ACT163 MC74ACT174 MC74ACT175 MC74ACT194 MC74ACT20 MC74ACT240 MC74ACT241 MC74ACT244 MC74ACT245 MC74ACT251 MC74ACT253 MC74ACT256 MC74ACT257 MC74ACT258 MC74ACT259 MC74ACT273 MC74ACT299 MC74ACT32 MC74ACT323 MC74ACT350 MC74ACT352 MC74ACT353 MC74ACT373 MC74ACT374 MC74ACT377 MC74ACT378 MC74ACT521 MC74ACT533 MC74ACT534 MC74ACT540 MC74ACT541 MC74ACT563 MC74ACT564 MC74ACT573 3.1-22 3.1-19 3.1-22 3.1-19 3.1-19 3.1-12 3.1-12 3.1-32 3.1-16 3.1-17 3.1-32 3.1-27 3.1-28 3.1-29 3.1-29 3.1-16 3.1-16 3.1-16 3.1-16 3.1-19 3.1-20 3.1-33 3.1-21 3.1-11 3.1-11 3.1-11 3.1-10 3.1-27 3.1-28 3.1-26 3.1-28 3.1-28 3.1-26 3.1-20 3.1-33 3.1-24 3.1-33 3.1-33 3.1-28 3.1-28 3.1-26 3.1-20 3.1-20 3.1-18 3.1-14 3.1-26 3.1-20 3.1-11 3.1-11 3.1-26 3.1-20 3.1-26
TTL, ECL, CMOS and Special Logic Circuits
3.1-40
Motorola Master Selection Guide
Device Index
MC74ACT574 MC74ACT620 MC74ACT623 MC74ACT640 MC74ACT643 MC74ACT646 MC74ACT648 MC74ACT652 MC74ACT74 MC74ACT810 MC74ACT86 MC74F00 MC74F02 MC74F04 MC74F08 MC74F10 MC74F109 MC74F11 MC74F112 MC74F1245 MC74F125 MC74F126 MC74F13 MC74F132 MC74F138 MC74F139 MC74F14 MC74F148 MC74F151 MC74F153 MC74F157A MC74F158A MC74F160A MC74F161A MC74F162A MC74F163A MC74F164 MC74F168 MC74F169 MC74F174 MC74F175 MC74F1803 MC74F181 MC74F182 MC74F194 MC74F195 MC74F20 MC74F21 MC74F2245 MC74F240 MC74F241 MC74F242 3.1-20 3.1-10 3.1-10 3.1-10 3.1-10 3.1-11 3.1-11 3.1-11 3.1-18 3.1-23 3.1-23 3.1-22 3.1-24 3.1-25 3.1-21 3.1-22 3.1-19 3.1-22 3.1-19 3.1-10 3.1-12 3.1-12 3.1-32 3.1-32 3.1-16 3.1-17 3.1-32 3.1-18 3.1-27 3.1-28 3.1-28 3.1-28 3.1-15 3.1-15 3.1-15 3.1-15 3.1-33 3.1-14 3.1-14 3.1-19 3.1-20 3.1-13 3.1-9 3.1-9 3.1-33 3.1-33 3.1-21 3.1-21 3.1-34 3.1-11 3.1-11 3.1-12 MC74F243 MC74F244 MC74F245 MC74F251 MC74F253 MC74F256 MC74F257A MC74F258A MC74F259 MC74F269 MC74F280 MC74F283 MC74F299 MC74F32 MC74F323 MC74F350 MC74F352 MC74F353 MC74F365 MC74F366 MC74F367 MC74F368 MC74F37 MC74F373 MC74F374 MC74F377 MC74F378 MC74F379 MC74F38 MC74F381 MC74F382 MC74F3893A MC74F398 MC74F399 MC74F40 MC74F51 MC74F521 MC74F533 MC74F534 MC74F537 MC74F538 MC74F539 MC74F544 MC74F568 MC74F569 MC74F574 MC74F579 MC74F620 MC74F623 MC74F64 MC74F640 MC74F646 3.1-12 3.1-11 3.1-10 3.1-27 3.1-28 3.1-26 3.1-29 3.1-29 3.1-26 3.1-15 3.1-30 3.1-9 3.1-33 3.1-24 3.1-33 3.1-33 3.1-28 3.1-28 3.1-10 3.1-10 3.1-10 3.1-10 3.1-21 3.1-26 3.1-20 3.1-20 3.1-32 3.1-21 3.1-22 3.1-9 3.1-9 3.1-34 3.1-29 3.1-29 3.1-21 3.1-23 3.1-14 3.1-26 3.1-20 3.1-16 3.1-16 3.1-16 3.1-11 3.1-14 3.1-14 3.1-20 3.1-15 3.1-11 3.1-11 3.1-22 3.1-11 3.1-11 MC74F657A MC74F657B MC74F74 MC74F779 MC74F803 MC74F823 MC74F827 MC74F828 MC74F85 MC74F86 MC74HC00A MC74HC02A MC74HC03A MC74HC04A MC74HC08A MC74HC10 MC74HC107 MC74HC109 MC74HC11 MC74HC112 MC74HC125A MC74HC132A MC74HC133 MC74HC137 MC74HC138A MC74HC139A MC74HC147 MC74HC14A MC74HC151 MC74HC153 MC74HC154 MC74HC157A MC74HC158 MC74HC158A MC74HC160 MC74HC161A MC74HC162 MC74HC163 MC74HC164 MC74HC164A MC74HC165 MC74HC173 MC74HC174A MC74HC175 MC74HC175A MC74HC194 MC74HC195 MC74HC20 MC74HC237 MC74HC240A MC74HC241A MC74HC242 3.1-10 3.1-10 3.1-19 3.1-15 3.1-13 3.1-10 3.1-10 3.1-10 3.1-14 3.1-23 3.1-22 3.1-24 3.1-22 3.1-25 3.1-21 3.1-22 3.1-19 3.1-19 3.1-22 3.1-19 3.1-12 3.1-32 3.1-21 3.1-16 3.1-16 3.1-17 3.1-18 3.1-32 3.1-27 3.1-28 3.1-16 3.1-28 3.1-28 3.1-28 3.1-15 3.1-15 3.1-15 3.1-15 3.1-33 3.1-33 3.1-33 3.1-21 3.1-19 3.1-21 3.1-21 3.1-33 3.1-33 3.1-21 3.1-16 3.1-11 3.1-11 3.1-12
Motorola Master Selection Guide
3.1-41
TTL, ECL, CMOS and Special Logic Circuits
Device Index
MC74HC244A MC74HC245A MC74HC251 MC74HC253 MC74HC257 MC74HC259 MC74HC27 MC74HC273A MC74HC280 MC74HC299 MC74HC30 MC74HC32A MC74HC354 MC74HC365 MC74HC366 MC74HC367 MC74HC368 MC74HC373A MC74HC374A MC74HC390 MC74HC393 MC74HC4002 MC74HC4016 MC74HC4017 MC74HC4020A MC74HC4024 MC74HC4040A MC74HC4046A MC74HC4049 MC74HC4050 MC74HC4051 MC74HC4052 MC74HC4053 MC74HC4060 MC74HC4060A MC74HC4066 MC74HC4075 MC74HC4078 MC74HC42 MC74HC4316 MC74HC4351 MC74HC4353 MC74HC4511 MC74HC4514 MC74HC4538A MC74HC4851A MC74HC4852A MC74HC4853A MC74HC51 MC74HC533A MC74HC534A MC74HC540A 3.1-12 3.1-12 3.1-27 3.1-28 3.1-28 3.1-16 3.1-24 3.1-20 3.1-30 3.1-33 3.1-21 3.1-24 3.1-27 3.1-10 3.1-10 3.1-10 3.1-10 3.1-27 3.1-20 3.1-15 3.1-15 3.1-24 3.1-29 3.1-15 3.1-14 3.1-29 3.1-14 3.1-35 3.1-25 3.1-25 3.1-27 3.1-28 3.1-29 3.1-14 3.1-14 3.1-29 3.1-25 3.1-23 3.1-16 3.1-29 3.1-27 3.1-29 3.1-17 3.1-16 3.1-29 3.1-27 3.1-27 3.1-27 3.1-22 3.1-27 3.1-20 3.1-11 MC74HC541A MC74HC563A MC74HC564A MC74HC573A MC74HC574A MC74HC58 MC74HC589 MC74HC589A MC74HC595A MC74HC597 MC74HC597A MC74HC640A MC74HC646 MC74HC688 MC74HC7266 MC74HC7266A MC74HC73 MC74HC74A MC74HC75 MC74HC76 MC74HC85 MC74HC86 MC74HC86A MC74HCT00A MC74HCT04A MC74HCT08A MC74HCT138A MC74HCT14A MC74HCT157A MC74HCT161A MC74HCT163A MC74HCT174A MC74HCT240A MC74HCT241A MC74HCT244A MC74HCT245A MC74HCT273A MC74HCT32A MC74HCT373A MC74HCT374A MC74HCT541A MC74HCT573A MC74HCT574A MC74HCT74A MC74HCU04 MC74HCU04A MC74LCX00 MC74LCX02 MC74LCX04 MC74LCX08 MC74LCX125 MC74LCX138 3.1-11 3.1-27 3.1-20 3.1-27 3.1-20 3.1-22 3.1-33 3.1-33 3.1-33 3.1-33 3.1-33 3.1-11 3.1-12 3.1-14 3.1-23 3.1-23 3.1-19 3.1-19 3.1-26 3.1-19 3.1-14 3.1-23 3.1-23 3.1-22 3.1-25 3.1-21 3.1-16 3.1-32 3.1-28 3.1-15 3.1-15 3.1-19 3.1-11 3.1-11 3.1-11 3.1-10 3.1-20 3.1-24 3.1-26 3.1-20 3.1-11 3.1-27 3.1-20 3.1-19 3.1-25 3.1-25 3.1-21 3.1-24 3.1-25 3.1-21 3.1-9 3.1-17 MC74LCX157 MC74LCX16240A MC74LCX16244 MC74LCX16245 MC74LCX16373 MC74LCX373 MC74LCX16374 MC74LCX16500 MC74LCX16501 MC74LCX16543A MC74LCX240 MC74LCX244 MC74LCX245 MC74LCX2952 MC74LCX32 MC74LCX374 MC74LCX540 MC74LCX541 MC74LCX573 MC74LCX574 MC74LCX652 MC74LCX86 MC74LVQ00 MC74LVQ04 MC74LVQ125 MC74LVQ138 MC74LVQ240 MC74LVQ244 MC74LVQ245 MC74LVQ32 MC74LVQ373 MC74LVQ374 MC74LVQ541 MC74LVQ573 MC74LVQ574 MC74LVQ646 MC74LVQ652 MC74LVX4245 MC74VHC02 MC74VHC04 MC74VHC08 MC74HC126A MC74VHC125 MC74VHC138 MC74VHC14 MC74VHC157 MC74VHC244 MC74VHC245 MC74VHC32 MC74VHC373 MC74VHC374 MC74VHC541 3.1-28 3.1-9 3.1-9 3.1-34 3.1-26 3.1-26 3.1-20 3.1-34 3.1-34 3.1-34 3.1-9 3.1-9 3.1-34 3.1-34 3.1-24 3.1-20 3.1-9 3.1-9 3.1-26 3.1-20 3.1-34 3.1-23 3.1-21 3.1-25 3.1-10 3.1-17 3.1-10 3.1-9 3.1-34 3.1-24 3.1-26 3.1-20 3.1-9 3.1-26 3.1-20 3.1-34 3.1-34 3.1-34 3.1-24 3.1-25 3.1-21 3.1-12 3.1-12 3.1-16 3.1-32 3.1-28 3.1-12 3.1-12 3.1-24 3.1-27 3.1-20 3.1-11
TTL, ECL, CMOS and Special Logic Circuits
3.1-42
Motorola Master Selection Guide
Device Index
MC74VHC573 MC74VHC574 MC74VHC595 MC74VHC74 MC830 MC832 MC836 MC837 MC840 MC844 MC845 MC846 MC88913 MC88914 MC88915*55 MC88915*70 MC88915T*100 MC88915T*133 MC88915T*160 MC88915T*55 MC88915T*70 MC88916*70 MC88916*80 MC88920 MC88921 MC88LV926 MC88PL117 MC936 MC937 MC944 MC945 MC946 MC951 MC952 MC953 MCCS142233 MCCS142235 MCCS142236 MCCS142237 MCCS142238 MCCS142239 MCH12140 MCK12140 MCM10143 MCM10145 MCM10146 MCM10152 MPA1016 MPA1036 MPA1064 MPA1100 MPA17128 3.1-27 3.1-20 3.1-33 3.1-19 3.1-21 3.1-9 3.1-25 3.1-25 3.1-25 3.1-18 3.1-18 3.1-22 3.1-13 3.1-13 3.1-13 3.1-13 3.1-13 3.1-13 3.1-13 3.1-13 3.1-13 3.1-13 3.1-13 3.1-13 3.1-13 3.1-13 3.1-13 3.1-25 3.1-25 3.1-18 3.1-18 3.1-22 3.1-29 3.1-19 3.1-19 3.1-32 3.1-32 3.1-32 3.1-32 3.1-32 3.1-32 3.1-17 3.1-17 3.1-32 3.1-32 3.1-31 3.1-31 3.1-18 3.1-18 3.1-18 3.1-18 3.1-32 MPA1765 MPC903 MPC904 MPC905 MPC911 MPC930 MPC931 MPC946 MPC947 MPC948 MPC948L MPC949 MPC950 MPC951 MPC952 MPC956 MPC970 MPC972 MPC973 MPC974 MPC980 MPC990 MPC991 MPC992 SN54LS00 SN54LS01 SN54LS02 SN54LS03 SN54LS04 SN54LS05 SN54LS08 SN54LS09 SN54LS10 SN54LS107A SN54LS109A SN54LS11 SN54LS112A SN54LS113A SN54LS114A SN54LS12 SN54LS122 SN54LS123 SN54LS125A SN54LS126A SN54LS13 SN54LS132 SN54LS133 SN54LS137 SN54LS138 SN54LS139 SN54LS14 SN54LS145 3.1-32 3.1-12 3.1-12 3.1-12 3.1-13 3.1-13 3.1-13 3.1-13 3.1-12 3.1-12 3.1-12 3.1-13 3.1-13 3.1-13 3.1-13 3.1-13 3.1-13 3.1-13 3.1-13 3.1-13 3.1-13 3.1-13 3.1-13 3.1-13 3.1-22 3.1-22 3.1-24 3.1-22 3.1-25 3.1-25 3.1-21 3.1-21 3.1-22 3.1-19 3.1-19 3.1-22 3.1-19 3.1-19 3.1-19 3.1-22 3.1-29 3.1-29 3.1-12 3.1-12 3.1-32 3.1-32 3.1-21 3.1-16 3.1-16 3.1-17 3.1-32 3.1-16 SN54LS147 SN54LS148 SN54LS15 SN54LS151 SN54LS153 SN54LS155 SN54LS156 SN54LS157 SN54LS158 SN54LS160A SN54LS161A SN54LS162A SN54LS163A SN54LS164 SN54LS165 SN54LS166 SN54LS168 SN54LS169 SN54LS170 SN54LS173A SN54LS174 SN54LS175 SN54LS190 SN54LS191 SN54LS192 SN54LS193 SN54LS194A SN54LS195A SN54LS196 SN54LS197 SN54LS20 SN54LS21 SN54LS22 SN54LS221 SN54LS240 SN54LS241 SN54LS242 SN54LS243 SN54LS244 SN54LS245 SN54LS247 SN54LS248 SN54LS249 SN54LS251 SN54LS253 SN54LS256 SN54LS257B SN54LS258B SN54LS259 SN54LS26 SN54LS260 SN54LS266 3.1-17 3.1-18 3.1-22 3.1-27 3.1-28 3.1-16 3.1-16 3.1-28 3.1-28 3.1-14 3.1-14 3.1-14 3.1-14 3.1-33 3.1-33 3.1-33 3.1-15 3.1-15 3.1-32 3.1-18 3.1-19 3.1-21 3.1-15 3.1-15 3.1-15 3.1-15 3.1-33 3.1-34 3.1-14 3.1-14 3.1-21 3.1-21 3.1-21 3.1-29 3.1-11 3.1-11 3.1-12 3.1-12 3.1-11 3.1-11 3.1-17 3.1-17 3.1-17 3.1-27 3.1-28 3.1-26 3.1-28 3.1-29 3.1-26 3.1-21 3.1-24 3.1-23
Motorola Master Selection Guide
3.1-43
TTL, ECL, CMOS and Special Logic Circuits
Device Index
SN54LS27 SN54LS273 SN54LS279 SN54LS28 SN54LS280 SN54LS283 SN54LS290 SN54LS293 SN54LS298 SN54LS299 SN54LS30 SN54LS32 SN54LS322A SN54LS323 SN54LS33 SN54LS348 SN54LS352 SN54LS353 SN54LS365A SN54LS366A SN54LS367A SN54LS368A SN54LS37 SN54LS373 SN54LS374 SN54LS375 SN54LS377 SN54LS378 SN54LS379 SN54LS38 SN54LS386 SN54LS390 SN54LS393 SN54LS398 SN54LS399 SN54LS40 SN54LS42 SN54LS47 SN54LS48 SN54LS490 SN54LS51 SN54LS54 SN54LS540 SN54LS541 SN54LS55 SN54LS569A SN54LS623 SN54LS640 SN54LS641 SN54LS642 SN54LS645 SN54LS669 3.1-24 3.1-20 3.1-27 3.1-24 3.1-30 3.1-9 3.1-15 3.1-14 3.1-28 3.1-33 3.1-21 3.1-24 3.1-33 3.1-33 3.1-24 3.1-18 3.1-28 3.1-28 3.1-10 3.1-10 3.1-10 3.1-10 3.1-21 3.1-26 3.1-20 3.1-26 3.1-20 3.1-19 3.1-18 3.1-22 3.1-23 3.1-15 3.1-15 3.1-29 3.1-29 3.1-21 3.1-16 3.1-17 3.1-17 3.1-15 3.1-23 3.1-22 3.1-11 3.1-11 3.1-22 3.1-14 3.1-11 3.1-11 3.1-34 3.1-34 3.1-11 3.1-16 SN54LS670 SN54LS682 SN54LS684 SN54LS688 SN54LS73A SN54LS748 SN54LS74A SN54LS75 SN54LS76A SN54LS77 SN54LS795 SN54LS796 SN54LS797 SN54LS798 SN54LS83A SN54LS848 SN54LS85 SN54LS86 SN54LS90 SN54LS92 SN54LS93 SN54LS95B SN74LS00 SN74LS01 SN74LS02 SN74LS03 SN74LS04 SN74LS05 SN74LS08 SN74LS09 SN74LS10 SN74LS107A SN74LS109A SN74LS11 SN74LS112A SN74LS113A SN74LS114A SN74LS12 SN74LS122 SN74LS123 SN74LS125A SN74LS126A SN74LS13 SN74LS132 SN74LS133 SN74LS136 SN74LS137 SN74LS138 SN74LS139 SN74LS14 SN74LS145 SN74LS147 3.1-32 3.1-14 3.1-14 3.1-14 3.1-19 3.1-18 3.1-19 3.1-26 3.1-19 3.1-26 3.1-10 3.1-10 3.1-10 3.1-10 3.1-9 3.1-18 3.1-14 3.1-23 3.1-15 3.1-15 3.1-14 3.1-33 3.1-22 3.1-22 3.1-24 3.1-22 3.1-25 3.1-25 3.1-21 3.1-21 3.1-22 3.1-19 3.1-19 3.1-22 3.1-19 3.1-19 3.1-19 3.1-22 3.1-29 3.1-29 3.1-12 3.1-12 3.1-32 3.1-32 3.1-21 3.1-23 3.1-16 3.1-16 3.1-17 3.1-32 3.1-16 3.1-17 SN74LS148 SN74LS15 SN74LS151 SN74LS153 SN74LS155 SN74LS156 SN74LS157 SN74LS158 SN74LS160A SN74LS161A SN74LS162A SN74LS163A SN74LS164 SN74LS165 SN74LS166 SN74LS168 SN74LS169 SN74LS170 SN74LS173A SN74LS174 SN74LS175 SN74LS190 SN74LS191 SN74LS192 SN74LS193 SN74LS194A SN74LS195A SN74LS196 SN74LS197 SN74LS20 SN74LS21 SN74LS22 SN74LS221 SN74LS240 SN74LS241 SN74LS242 SN74LS243 SN74LS244 SN74LS245 SN74LS247 SN74LS248 SN74LS249 SN74LS251 SN74LS253 SN74LS257B SN74LS258B SN74LS259 SN74LS26 SN74LS260 SN74LS266 SN74LS27 SN74LS273 3.1-18 3.1-22 3.1-27 3.1-28 3.1-16 3.1-16 3.1-28 3.1-28 3.1-14 3.1-14 3.1-14 3.1-14 3.1-33 3.1-33 3.1-33 3.1-15 3.1-15 3.1-32 3.1-18 3.1-19 3.1-21 3.1-15 3.1-15 3.1-15 3.1-15 3.1-33 3.1-34 3.1-14 3.1-14 3.1-21 3.1-21 3.1-21 3.1-29 3.1-11 3.1-11 3.1-12 3.1-12 3.1-11 3.1-11 3.1-17 3.1-17 3.1-17 3.1-27 3.1-28 3.1-28 3.1-29 3.1-26 3.1-21 3.1-24 3.1-23 3.1-24 3.1-20
TTL, ECL, CMOS and Special Logic Circuits
3.1-44
Motorola Master Selection Guide
Device Index
SN74LS279 SN74LS28 SN74LS280 SN74LS283 SN74LS290 SN74LS293 SN74LS298 SN74LS299 SN74LS30 SN74LS32 SN74LS322A SN74LS323 SN74LS33 SN74LS348 SN74LS352 SN74LS353 SN74LS365A SN74LS366A SN74LS367A SN74LS368A SN74LS37 SN74LS373 SN74LS374 SN74LS375 SN74LS377 3.1-27 3.1-24 3.1-30 3.1-9 3.1-15 3.1-14 3.1-28 3.1-33 3.1-21 3.1-24 3.1-33 3.1-33 3.1-24 3.1-18 3.1-28 3.1-28 3.1-10 3.1-10 3.1-10 3.1-10 3.1-21 3.1-26 3.1-20 3.1-26 3.1-20 SN74LS378 SN74LS379 SN74LS38 SN74LS386 SN74LS390 SN74LS393 SN74LS395 SN74LS398 SN74LS399 SN74LS40 SN74LS42 SN74LS47 SN74LS48 SN74LS490 SN74LS51 SN74LS54 SN74LS540 SN74LS541 SN74LS55 SN74LS569A SN74LS623 SN74LS640 SN74LS641 SN74LS642 3.1-19 3.1-18 3.1-22 3.1-23 3.1-15 3.1-15 3.1-33 3.1-29 3.1-29 3.1-21 3.1-16 3.1-17 3.1-17 3.1-15 3.1-23 3.1-22 3.1-11 3.1-11 3.1-22 3.1-14 3.1-11 3.1-11 3.1-34 3.1-34 SN74LS645 SN74LS669 SN74LS670 SN74LS682 SN74LS684 SN74LS688 SN74LS73A SN74LS748 SN74LS74A SN74LS75 SN74LS76A SN74LS77 SN74LS795 SN74LS796 SN74LS797 SN74LS798 SN74LS83A SN74LS848 SN74LS85 SN74LS86 SN74LS90 SN74LS92 SN74LS93 SN74LS95B 3.1-11 3.1-16 3.1-32 3.1-14 3.1-14 3.1-14 3.1-19 3.1-18 3.1-19 3.1-26 3.1-19 3.1-26 3.1-10 3.1-10 3.1-10 3.1-10 3.1-9 3.1-18 3.1-14 3.1-23 3.1-15 3.1-15 3.1-14 3.1-33
Motorola Master Selection Guide
3.1-45
TTL, ECL, CMOS and Special Logic Circuits
Ordering Information Device Nomenclatures
LS - Low Power Schottky SN
Standard Prefix Temperature Range * 74 Series (0 to +70C) * 54 Series (-55 to +125C) Family * LS = Low Power Schottky
VV
WW
XXXX
Y
Package Type * N for Plastic (74 Series Only) * J for Ceramic * D for 150 mil Plastic SOIC (74 Series Only) * DW for 300 mil Plastic SOIC (74 Series Only) Function Type
FAST MC
Motorola Circuit Identifier Temperature Range * 74 Series (0 to +70C) Family * F = FAST
VV
W
XXXX
Y
Package Type * N for Plastic (74 Series Only) * D for 150 mil Plastic SOIC (74 Series Only) * DW for 300 mil Plastic SOIC (74 Series Only) * SD for Plastic SSOP Function Type
MECL 10K, MECL 10H/100H MC
Motorola Circuit Identifier Temperature Range * 10 = 10K (-30 to +85C) * 10H = 10H (0 to +75C) * 100H = 100K Compatible (0 to +85C)
WWW
XXX
YY
Package Type * P for Plastic * L for Ceramic * FN for PLCC
Function Type
TTL, ECL, CMOS and Special Logic Circuits
3.1-46
Motorola Master Selection Guide
ECLinPS, ECLinPS Lite MC
Motorola Circuit Identifier * MC = Fully Qualified Circuit * XC = Non Reliability Qualified Compatibility Identifier * 10 = 10H Compatible (0 to +85C) * 100 = 100K Compatible (0 to +85C)
WWW
XXX
YYY
ZZ
Package Type * FN = PLCC * D = Plastic SOIC * L = Ceramic DIP * P = Plastic DIP Function Type * YYY = 3-Digits for ECLinPS * YY= 2-Digits for ECLinPS Lite ECLinPS Family Identifier * E = ECLinPS * EL = ECLinPS Lite * ELT = ECLinPS Lite Translator * LVE = Low Voltage ECLinPS * LVEL = Low Voltage ECLinPS Lite
Metal Gate 14000 Series CMOS MC
Motorola Circuit Identifier Function Type Identifier (per JEDEC Standard) * B (or Blank)= Buffered Outputs * UB = Unbuffered Outputs
14XXX YY
ZZ
Package and Temperature Range * CL for Ceramic -55 to +125C * CP for Plastic -55 to +125C * D/DW for Small Outline Package (Plastic) -55 to +125C * DT for Plastic TSSOP
High-Speed CMOS MC
Motorola Circuit Identifier Temperature Range * 74 Series (-55 to +125C) * 54 Series (-55 to +125C) High-Speed CMOS Specification Identifier * HC = Buffered High-Speed CMOS * HCU = Unbuffered High-Speed CMOS* * HCT = High-Speed CMOS TTL Compatible *Not Available On All Devices
VV
WWW
XXXX
Y
Package Type * N for Plastic (74 Series Only) * J for Ceramic (54 Series Only) * D for 150 mil Plastic SOIC (74 Series Only) * DW for 300 mil Plastic SOIC (74 Series Only) * SD for Plastic SSOP * DT for Plastic TSSOP Function Type * XX(X) Same Function and Pin Configuration as LSTTL * 4XXX Same Function and Pin Configuration as CMOS 14000 * 7XX(X) Variation of LSTTL or CMOS 14000 Device
FACT MC
Motorola Circuit Identifier Temperature Range Family * 74AC = FACT (-40 to +85C) * 74ACT = TTL Compatible (-40 to +85C)
WWWWW
XXX
YY
Package Type * N for Plastic * D for Narrow SOIC * DW for Wide SOIC * SD for Plastic SSOP * DT for Plastic TSSOP Function Type
Motorola Master Selection Guide
3.1-47
TTL, ECL, CMOS and Special Logic Circuits
Other Logic Circuits MC/MCCS WWWWWW X YY ZZ
Package Type * N for Plastic * D for Narrow SOIC * FN for PLCC * FJ for CLCC Option Type Motorola Circuit Identifier * MC = Standard Circuit Identifier * MCCS = Circuit Chip-Set Identifier Function Type Option Suffix Indicator
MECL III/HTL/DTL MC
Motorola Circuit Identifier
XXXX
Y
Package Type * P for Plastic * L for Ceramic * D for Narrow SOIC * FN for PLCC Function Type
LCX Products MC
Motorola Circuit Identifier Temperature Range * 74 = -40 to +85C Family Identifier * LCX = 5V-Tolerant Low-Voltage CMOS
74
LCX
YYYYY
ZZ
Package Type * D for Plastic Narrow JEDEC SOIC * DW for Plastic Wide JEDEC SOIC * M for Plastic EIAJ SOIC * SD for Plastic SSOP * DT for Plastic TSSOP Function Type
LVQ Products MC
Motorola Circuit Identifier Temperature Range * 74 = -40 to +85C Family Identifier * LVQ =Low-Voltage Quiet CMOS
74
LVQ
YYYY
ZZ
Package Type * D for Plastic Narrow JEDEC SOIC * DW for Plastic Wide JEDEC SOIC * M for Plastic EIAJ SOIC * SD for Plastic SSOP * DT for Plastic TSSOP Function Type
TTL, ECL, CMOS and Special Logic Circuits
3.1-48
Motorola Master Selection Guide
Motorola Programmable Arrays (MPA)
FPGA Nomenclature
MPA1 XXX YY Z I
Motorola Programmable Array (First Series) Circuit Identifier Number of Core Cells Physical Number of Cells in 100's * 016 = 1,600 Cells * 036 = 3,600 Cells * 064 = 6,400 Cells * 100 = 10,000 Cells Temperature Grade * Blank = Commercial * I = Industrial Speed Grade Package Type * FN = 84 PLCC * DD = 128 PQFP * DH = 160 PQFP * DK = 208 PQFP * HI = 181 CPGA * KE = 224 CPGA * HV = 299 CPGA * BG = 256 PBGA
EPROM/EEPROM Nomenclature
MPA17 C XXX YY I
Motorola EPROM/EEPROM Circuit Identifier PROM Type * Blank = EPROM * C = EEPROM Number of Memory Bits (in K) Temperature Grade * Blank = Commercial * I = Industrial Package Type * D = SOIC * P = PDIP * FN = PLCC
Motorola Master Selection Guide
3.1-49
TTL, ECL, CMOS and Special Logic Circuits
Case Outlines
8-Pin Packages
P SUFFIX PLASTIC DIP PACKAGE CASE 626-05 ISSUE K
8
5
-B-
1 4 NOTES: 1. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 2. PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CORNERS). 3. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
F
NOTE 2
-A- L
C -T-
SEATING PLANE
J N D K
M
M
H
G 0.13 (0.005) TA
M
B
M
DIM A B C D F G H J K L M N
MILLIMETERS MIN MAX 9.40 10.16 6.10 6.60 3.94 4.45 0.38 0.51 1.02 1.78 2.54 BSC 0.76 1.27 0.20 0.30 2.92 3.43 7.62 BSC --- 10_ 0.76 1.01
INCHES MIN MAX 0.370 0.400 0.240 0.260 0.155 0.175 0.015 0.020 0.040 0.070 0.100 BSC 0.030 0.050 0.008 0.012 0.115 0.135 0.300 BSC --- 10_ 0.030 0.040
D SUFFIX PLASTIC SOIC PACKAGE CASE 751-05 ISSUE S
A
8
D
5
C
E
1 4
H
0.25
M
B
M
h B C e A
SEATING PLANE
X 45 _
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS ARE IN MILLIMETERS. 3. DIMENSION D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE MOLD PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A A1 B C D E e H h L MILLIMETERS MIN MAX 1.35 1.75 0.10 0.25 0.35 0.49 0.18 0.25 4.80 5.00 3.80 4.00 1.27 BSC 5.80 6.20 0.25 0.50 0.40 1.25 0_ 7_
q
L 0.10 A1 0.25 B
M
CB
S
A
S
q
TTL, ECL, CMOS and Special Logic Circuits
3.1-50
Motorola Master Selection Guide
8-Pin Packages
SD SUFFIX PLASTIC SSOP PACKAGE CASE 940-03 ISSUE B
8X
K REF 0.12 (0.005)
0.25 (0.010)
M
TU
S
V
S
N M
L/2 L
PIN 1 IDENT 1
8
5
N F B DETAIL E
4
A -V- 0.20 (0.008)
M
-U-
J
TU
S
0.076 (0.003) -T-
SEATING PLANE
C D G H
DETAIL E
14-Pin Packages
L,J SUFFIX CERAMIC DIP PACKAGE CASE 632-08 ISSUE Y
9
-A-
14
-B-
1 7
C
-T-
SEATING PLANE
K F D
14 PL
G 0.25 (0.010)
M
N J TA
S 14 PL
Motorola Master Selection Guide
CCCC EEE CCCC EEE CCCC
K1 L M 0.25 (0.010)
M
K
J1
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION/INTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF K DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR INTRUSION SHALL NOT REDUCE DIMENSION K BY MORE THAN 0.07 (0.002) AT LEAST MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 2.87 3.13 5.20 5.38 1.73 1.99 0.05 0.21 0.63 0.95 0.65 BSC 0.44 0.60 0.09 0.20 0.09 0.16 0.25 0.38 0.25 0.33 7.65 7.90 0_ 8_ INCHES MIN MAX 0.113 0.123 0.205 0.212 0.068 0.078 0.002 0.008 0.024 0.037 0.026 BSC 0.017 0.023 0.003 0.008 0.003 0.006 0.010 0.015 0.010 0.013 0.301 0.311 0_ 8_
SECTION N-N
-W-
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. DIM A B C D F G J K L M N INCHES MIN MAX 0.750 0.785 0.245 0.280 0.155 0.200 0.015 0.020 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15_ 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.94 6.23 7.11 3.94 5.08 0.39 0.50 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15_ 0.51 1.01
TB
S
3.1-51
TTL, ECL, CMOS and Special Logic Circuits
14-Pin Packages
P,N SUFFIX PLASTIC DIP PACKAGE CASE 646-06 ISSUE M
14
8
B
1 7
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M N INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.290 0.310 --- 10_ 0.015 0.039 MILLIMETERS MIN MAX 18.16 18.80 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.37 7.87 --- 10_ 0.38 1.01
A F N -T-
SEATING PLANE
L C
K H G D 14 PL 0.13 (0.005)
M
J M
D SUFFIX PLASTIC SOIC PACKAGE CASE 751A-03 ISSUE F
-A-
14 8
-B-
1 7
P 7 PL 0.25 (0.010)
M
B
M
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.
G C
R X 45 _
F
-T-
SEATING PLANE
D 14 PL 0.25 (0.010)
K
M
M
S
J
TB
A
S
DIM A B C D F G J K M P R
MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50
INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019
TTL, ECL, CMOS and Special Logic Circuits
3.1-52
Motorola Master Selection Guide
14-Pin Packages
M SUFFIX PLASTIC SOIC EIAJ PACKAGE CASE 965-01 ISSUE O
14
8
LE Q1 E HE M_ L DETAIL P
1
7
Z D e A VIEW P
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE 0.50 LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 1.42 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.056
c
b 0.13 (0.005)
M
A1 0.10 (0.004)
SD SUFFIX PLASTIC SSOP PACKAGE CASE 940A-03 ISSUE B
14X
K REF 0.12 (0.005)
M
TU
S
V
S
0.25 (0.010) N
L/2 L
PIN 1 IDENT 1
14
8
M B
7
N F DETAIL E
0.20 (0.008)
M
TU
S
J
0.076 (0.003) -T-
SEATING PLANE
C D G H
DETAIL E
Motorola Master Selection Guide
3.1-53
CCCC EEEE CCCC EEEE CCCC
K1 SECTION N-N
A -V-
-U-
K
J1
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION/INTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF K DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR INTRUSION SHALL NOT REDUCE DIMENSION K BY MORE THAN 0.07 (0.002) AT LEAST MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 6.07 6.33 5.20 5.38 1.73 1.99 0.05 0.21 0.63 0.95 0.65 BSC 1.08 1.22 0.09 0.20 0.09 0.16 0.25 0.38 0.25 0.33 7.65 7.90 0_ 8_ INCHES MIN MAX 0.238 0.249 0.205 0.212 0.068 0.078 0.002 0.008 0.024 0.037 0.026 BSC 0.042 0.048 0.003 0.008 0.003 0.006 0.010 0.015 0.010 0.013 0.301 0.311 0_ 8_
-W-
TTL, ECL, CMOS and Special Logic Circuits
14-Pin Packages
DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948G-01 ISSUE O
14X K REF
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
N
2X
L/2
14
8
0.25 (0.010) M
L
PIN 1 IDENT. 1 7
B -U-
N F DETAIL E K K1 J J1
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.50 0.60 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.020 0.024 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
0.15 (0.006) T U
S
A -V-
C 0.10 (0.004) -T- SEATING
PLANE
D
G
H
DETAIL E
16-Pin Packages
L,J SUFFIX CERAMIC DIP PACKAGE CASE 620-10 ISSUE V
-A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. DIM A B C D E F G H K L M N INCHES MIN MAX 0.750 0.785 0.240 0.295 --- 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 --- 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15 _ 0.51 1.01
-B-
1 8
C
L
-T-
SEATING PLANE
N E F D G
16 PL
K M J
16 PL
0.25 (0.010)
M
0.25 (0.010)
TA
S
TTL, ECL, CMOS and Special Logic Circuits
3.1-54
CCC EE CCC EE
M
SECTION N-N -W-
TB
S
Motorola Master Selection Guide
16-Pin Packages
P,N SUFFIX PLASTIC DIP PACKAGE CASE 648-08 ISSUE R
-A-
16 9
B
1 8
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01
F S
C
L
-T- H G D
16 PL
SEATING PLANE
K
J TA
M
M
0.25 (0.010)
M
DIM A B C D F G H J K L M S
D SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05 ISSUE J
-A-
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019
16
9
-B-
1 8
P
8 PL
0.25 (0.010)
M
B
S
G F
K C -T-
SEATING PLANE
R
X 45 _
M D
16 PL M
J
0.25 (0.010)
TB
S
A
S
DIM A B C D F G J K M P R
Motorola Master Selection Guide
3.1-55
TTL, ECL, CMOS and Special Logic Circuits
16-Pin Packages
DW SUFFIX PLASTIC WIDE SOIC PACKAGE CASE 751G-02 ISSUE A
-A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSIOM D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 10.15 10.45 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 0.25 0.32 0.10 0.25 0_ 7_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.400 0.411 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.004 0.009 0_ 7_ 0.395 0.415 0.010 0.029
-B-
1 8
8X
P 0.010 (0.25)
M
B
M
16X
D
M
J TA
S
0.010 (0.25)
B
S
F R X 45_ C -T-
14X DIM A B C D F G J K M P R
G
K
SEATING PLANE
M
M SUFFIX PLASTIC SOIC EIAJ PACKAGE CASE 966-01 ISSUE O
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018).
16
9
LE Q1 E HE M_ L DETAIL P
1
8
Z D e A VIEW P
c
b 0.13 (0.005)
M
A1 0.10 (0.004)
DIM A A1 b c D E e HE L LE M Q1 Z
MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 0.78
INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.031
TTL, ECL, CMOS and Special Logic Circuits
3.1-56
Motorola Master Selection Guide
16-Pin Packages
SD SUFFIX PLASTIC SSOP PACKAGE CASE 940B-03 ISSUE B
16X
K REF 0.12 (0.005)
M
TU
S
V
S
0.25 (0.010) N
L/2 L
PIN 1 IDENT
16
9
M B N F
1
8
DETAIL E K -U- J
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION/INTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF K DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR INTRUSION SHALL NOT REDUCE DIMENSION K BY MORE THAN 0.07 (0.002) AT LEAST MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 6.07 6.33 5.20 5.38 1.73 1.99 0.05 0.21 0.63 0.95 0.65 BSC 0.73 0.90 0.09 0.20 0.09 0.16 0.25 0.38 0.25 0.33 7.65 7.90 0_ 8_ INCHES MIN MAX 0.238 0.249 0.205 0.212 0.068 0.078 0.002 0.008 0.024 0.037 0.026 BSC 0.028 0.035 0.003 0.008 0.003 0.006 0.010 0.015 0.010 0.013 0.301 0.311 0_ 8_
A -V- 0.20 (0.008)
M
TU
S
0.076 (0.003) -T-
SEATING PLANE
C D G H
DETAIL E
DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948F-01 ISSUE O
16X K REF
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
2X
L/2
16
9
J1 B -U-
L
PIN 1 IDENT. 1 8
SECTION N-N J N 0.25 (0.010) M
0.15 (0.006) T U
S
A -V-
N F DETAIL E
C 0.10 (0.004) -T- SEATING
PLANE
H D G
DETAIL E
Motorola Master Selection Guide
3.1-57
CC EE CC EE CC
EEEE CCCC EEEE CCCC
K1 SECTION N-N -W-
J1
DIM A B C D F G H J J1 K K1 L M
K K1
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
-W-
DIM A B C D F G H J J1 K K1 L M
TTL, ECL, CMOS and Special Logic Circuits
18-Pin Packages
L,J SUFFIX CERAMIC DIP PACKAGE CASE 726-04 ISSUE G
-A-
18 10 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F FOR FULL LEADS. HALF LEADS OPTIONAL AT LEAD POSITIONS 1, 9, 10, AND 18. DIM A B C D F G J K L M N INCHES MIN MAX 0.880 0.910 0.240 0.295 --- 0.200 0.015 0.021 0.055 0.070 0.100 BSC 0.008 0.012 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 22.35 23.11 6.10 7.49 --- 5.08 0.38 0.53 1.40 1.78 2.54 BSC 0.20 0.30 3.18 4.32 7.62 BSC 0_ 15_ 0.51 1.02
-B-
1 9 OPTIONAL LEAD CONFIGURATION (1, 9, 10, 18)
L C N -T-
SEATING PLANE
K F G D 18 PL 0.25 (0.010) J
M 18 PL M
M
TA
S
0.25 (0.010)
TB
S
P,N SUFFIX PLASTIC DIP PACKAGE CASE 707-02 ISSUE C
18 1
10
B
9
NOTES: 1. POSITIONAL TOLERANCE OF LEADS (D), SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. MILLIMETERS MIN MAX 22.22 23.24 6.10 6.60 3.56 4.57 0.36 0.56 1.27 1.78 2.54 BSC 1.02 1.52 0.20 0.30 2.92 3.43 7.62 BSC 0_ 15_ 0.51 1.02 INCHES MIN MAX 0.875 0.915 0.240 0.260 0.140 0.180 0.014 0.022 0.050 0.070 0.100 BSC 0.040 0.060 0.008 0.012 0.115 0.135 0.300 BSC 0_ 15 _ 0.020 0.040
A C L
DIM A B C D F G H J K L M N
N F H G D
SEATING PLANE
K M J
TTL, ECL, CMOS and Special Logic Circuits
3.1-58
Motorola Master Selection Guide
20-Pin Packages
L,J SUFFIX CERAMIC DIP PACKAGE CASE 732-03 ISSUE E
20 1
11 10
B A F C L
NOTES: 1. LEADS WITHIN 0.25 (0.010) DIAMETER, TRUE POSITION AT SEATING PLANE, AT MAXIMUM MATERIAL CONDITION. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSIONS A AND B INCLUDE MENISCUS. MILLIMETERS MIN MAX 23.88 25.15 6.60 7.49 3.81 5.08 0.38 0.56 1.40 1.65 2.54 BSC 0.51 1.27 0.20 0.30 3.18 4.06 7.62 BSC 0_ 15 _ 0.25 1.02 INCHES MIN MAX 0.940 0.990 0.260 0.295 0.150 0.200 0.015 0.022 0.055 0.065 0.100 BSC 0.020 0.050 0.008 0.012 0.125 0.160 0.300 BSC 0_ 15_ 0.010 0.040
N H D
SEATING PLANE
G
K
J M
DIM A B C D F G H J K L M N
-A-
20 11
P,N SUFFIX PLASTICC DIP PACKAGE CASE 738-03 ISSUE E
B
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. INCHES MIN MAX 1.010 1.070 0.240 0.260 0.150 0.180 0.015 0.022 0.050 BSC 0.050 0.070 0.100 BSC 0.008 0.015 0.110 0.140 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27 BSC 1.27 1.77 2.54 BSC 0.21 0.38 2.80 3.55 7.62 BSC 0_ 15_ 0.51 1.01
1
10
C
-T-
SEATING PLANE
K M E G F D
20 PL
N J 0.25 (0.010)
M 20 PL
0.25 (0.010) TA
M
M
TB
M
DIM A B C D E F G J K L M N
-A-
20 11
DW SUFFIX PLASTIC WIDE SOIC PACKAGE CASE 751D-04 ISSUE E
-B-
1 10
10X
P 0.010 (0.25)
M
B
M
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.150 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 12.65 12.95 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 0.25 0.32 0.10 0.25 0_ 7_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.499 0.510 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.004 0.009 0_ 7_ 0.395 0.415 0.010 0.029
20X
D
M
J TA
S
0.010 (0.25)
B
S
F R X 45 _ C -T-
18X SEATING PLANE
G
K
M
Motorola Master Selection Guide
3.1-59
TTL, ECL, CMOS and Special Logic Circuits
20-Pin Packages
M SUFFIX PLASTIC SOIC EIAJ PACKAGE CASE 967-01 ISSUE O
20
11
LE Q1 M_ L DETAIL P
E HE
1
10
Z D e VIEW P A
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.18 0.27 12.35 12.80 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 0.81 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.486 0.504 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.032
c
b 0.13 (0.005)
M
A1 0.10 (0.004)
SD SUFFIX PLASTIC SSOP PACKAGE CASE 940C-03 ISSUE B
20X
K REF 0.12 (0.005)
M
TU
S
V
S
0.25 (0.010) N L/2 L
PIN 1 IDENT 1 10 20 11
M B N F DETAIL E A -V- 0.20 (0.008)
M
-U-
TU
S
J
0.076 (0.003) -T-
SEATING PLANE
C D G H
DETAIL E
TTL, ECL, CMOS and Special Logic Circuits
3.1-60
CCCC EEEE CCCC EEEE CCCC
K1
K
J1
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION/INTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF K DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR INTRUSION SHALL NOT REDUCE DIMENSION K BY MORE THAN 0.07 (0.002) AT LEAST MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 7.07 7.33 5.20 5.38 1.73 1.99 0.05 0.21 0.63 0.95 0.65 BSC 0.59 0.75 0.09 0.20 0.09 0.16 0.25 0.38 0.25 0.33 7.65 7.90 0_ 8_ INCHES MIN MAX 0.278 0.288 0.205 0.212 0.068 0.078 0.002 0.008 0.024 0.037 0.026 BSC 0.023 0.030 0.003 0.008 0.003 0.006 0.010 0.015 0.010 0.013 0.301 0.311 0_ 8_
SECTION N-N -W-
Motorola Master Selection Guide
20-Pin Packages
DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948E-02 ISSUE A
20X
K REF
M
0.15 (0.006) T U
S
0.10 (0.004)
TU
S
V
S
2X
L/2
20
11
B L
PIN 1 IDENT 1 10
J J1
-U-
SECTION N-N 0.25 (0.010)
N 0.15 (0.006) T U
S
A -V- N F
C D 0.100 (0.004) -T- SEATING
PLANE
G
H
DETAIL E
Motorola Master Selection Guide
3.1-61
III III III
M DETAIL E
K K1
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
-W-
DIM A B C D F G H J J1 K K1 L M
TTL, ECL, CMOS and Special Logic Circuits
20-Pin Packages
FN SUFFIX PLASTIC PLCC PACKAGE CASE 775-02 ISSUE C
B -N- Y BRK D -L- -M- W D Z
0.007 (0.180) M T L-M U
S
N
S S
0.007 (0.180) M T L-M
N
S
20
1
X V VIEW D-D
G1
0.010 (0.250)
S
T L-M
S
N
S
A Z R
0.007 (0.180) M T L-M 0.007 (0.180) M T L-M
S
N N
S
S
S
H
0.007 (0.180) M T L-M
S
N
S
C
E 0.004 (0.100) G G1 0.010 (0.250) S T L-M J -T-
SEATING PLANE
K1 K F VIEW S 0.007 (0.180)
M
VIEW S
S
T L-M
S
N
S
N
S
NOTES: 1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635).
DIM A B C E F G H J K R U V W X Y Z G1 K1
INCHES MIN MAX 0.385 0.395 0.385 0.395 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 --- 0.025 --- 0.350 0.356 0.350 0.356 0.042 0.048 0.042 0.048 0.042 0.056 --- 0.020 2_ 10 _ 0.310 0.330 0.040 ---
MILLIMETERS MIN MAX 9.78 10.03 9.78 10.03 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 --- 0.64 --- 8.89 9.04 8.89 9.04 1.07 1.21 1.07 1.21 1.07 1.42 --- 0.50 2_ 10 _ 7.88 8.38 1.02 ---
TTL, ECL, CMOS and Special Logic Circuits
3.1-62
Motorola Master Selection Guide
24-Pin Packages
J SUFFIX CERAMIC DIP PACKAGE CASE 758-02 ISSUE A
B
24 13
L
P
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL.
1
12
-A- N C K G F D 24 PL 0.25 (0.010)
M
J
-T-
SEATING PLANE
DIM A B C D F G J K L N P
INCHES MIN MAX 1.240 1.285 0.285 0.305 0.160 0.200 0.015 0.021 0.045 0.062 0.100 BSC 0.008 0.013 0.100 0.165 0.300 0.310 0.020 0.050 0.360 0.400
MILLIMETERS MIN MAX 31.50 32.64 7.24 7.75 4.07 5.08 0.38 0.53 1.14 1.57 2.54 BSC 0.20 0.33 2.54 4.19 7.62 7.87 0.51 1.27 9.14 10.16
TA
M
L,J,JW SUFFIX CERAMIC DIP PACKAGE CASE 623-05 ISSUE M
24
13
B
1 12
NOTES: 1. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 2. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE POSITION AT SEATING PLANE AT MAXIMUM MATERIAL CONDITION (WHEN FORMED PARALLEL). DIM A B C D F G J K L M N MILLIMETERS MIN MAX 31.24 32.77 12.70 15.49 4.06 5.59 0.41 0.51 1.27 1.52 2.54 BSC 0.20 0.30 3.18 4.06 15.24 BSC 0_ 15 _ 0.51 1.27 INCHES MIN MAX 1.230 1.290 0.500 0.610 0.160 0.220 0.016 0.020 0.050 0.060 0.100 BSC 0.008 0.012 0.125 0.160 0.600 BSC 0_ 15_ 0.020 0.050
A
SEATING PLANE
F
C
L G D N K M J
Motorola Master Selection Guide
3.1-63
TTL, ECL, CMOS and Special Logic Circuits
24-Pin Packages
N SUFFIX PLASTIC DIP PACKAGE CASE 709-02 ISSUE C
24 13
B
1 12
NOTES: 1. POSITIONAL TOLERANCE OF LEADS (D), SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. DIM A B C D F G H J K L M N MILLIMETERS MIN MAX 31.37 32.13 13.72 14.22 3.94 5.08 0.36 0.56 1.02 1.52 2.54 BSC 1.65 2.03 0.20 0.38 2.92 3.43 15.24 BSC 0_ 15_ 0.51 1.02 INCHES MIN MAX 1.235 1.265 0.540 0.560 0.155 0.200 0.014 0.022 0.040 0.060 0.100 BSC 0.065 0.080 0.008 0.015 0.115 0.135 0.600 BSC 0_ 15_ 0.020 0.040
A N K H G F D
SEATING PLANE
C
L
M
J
-A-
24 1 13
P,N SUFFIX PLASTIC DIP PACKAGE CASE 724-03 ISSUE D
NOTES: 1. CHAMFERED CONTOUR OPTIONAL. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 4. CONTROLLING DIMENSION: INCH.
-B-
12
C -T-
SEATING PLANE
L
K E G F D
24 PL
NOTE 1
N J
24 PL
M
0.25 (0.010)
M
M
TB
M
0.25 (0.010)
TA
M
DIM A B C D E F G J K L M N
INCHES MIN MAX 1.230 1.265 0.250 0.270 0.145 0.175 0.015 0.020 0.050 BSC 0.040 0.060 0.100 BSC 0.007 0.012 0.110 0.140 0.300 BSC 0_ 15_ 0.020 0.040
MILLIMETERS MIN MAX 31.25 32.13 6.35 6.85 3.69 4.44 0.38 0.51 1.27 BSC 1.02 1.52 2.54 BSC 0.18 0.30 2.80 3.55 7.62 BSC 0_ 15_ 0.51 1.01
P
24
A
13
P,N,PW SUFFIX PLASTIC DIP PACKAGE CASE 649-03 ISSUE D
NOTES: 1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE POSITION AT SEATING PLANE AT MAXIMUM MATERIAL CONDITION. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. MILLIMETERS MIN MAX 31.50 32.13 13.21 13.72 4.70 5.21 0.38 0.51 1.02 1.52 2.54 BSC 1.65 2.16 0.20 0.30 2.92 3.43 14.99 15.49 --- 10 0.51 1.02 0.13 0.38 0.51 0.76 INCHES MIN MAX 1.240 1.265 0.520 0.540 0.185 0.205 0.015 0.020 0.040 0.060 0.100 BSC 0.065 0.085 0.008 0.012 0.115 0.135 0.590 0.610 --- 10 _ 0.020 0.040 0.005 0.015 0.020 0.030
Q
B
1 12 DIM A B C D F G H J K L M N P Q
H F N K G D
SEATING PLANE
C
L
J
M
TTL, ECL, CMOS and Special Logic Circuits
3.1-64
Motorola Master Selection Guide
24-Pin Packages
DW SUFFIX PLASTIC WIDE SOIC PACKAGE CASE 751E-04 ISSUE E
-A-
24 13 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 15.25 15.54 7.40 7.60 2.35 2.65 0.35 0.49 0.41 0.90 1.27 BSC 0.23 0.32 0.13 0.29 0_ 8_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.601 0.612 0.292 0.299 0.093 0.104 0.014 0.019 0.016 0.035 0.050 BSC 0.009 0.013 0.005 0.011 0_ 8_ 0.395 0.415 0.010 0.029
-B-
12X
P 0.010 (0.25)
M
B
M
1
12
24X
D 0.010 (0.25)
M
J TA
S
B
S
F R C -T-
SEATING PLANE X 45 _
M
22X
G
K
DIM A B C D F G J K M P R
SD SUFFIX PLASTIC SSOP PACKAGE CASE 940D-03 ISSUE B
24X
K REF 0.12 (0.005)
M
TU
S
V
S
K L/2 L
PIN 1 IDENT 1 12 24 13
J B
J1
K1
SECTION N-N
A -V- 0.20 (0.008)
M
-U- N
S
0.25 (0.010)
TU
M N F DETAIL E
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION/INTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF K DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR INTRUSION SHALL NOT REDUCE DIMENSION K BY MORE THAN 0.07 (0.002) AT LEAST MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 8.07 8.33 5.20 5.38 1.73 1.99 0.05 0.21 0.63 0.95 0.65 BSC 0.44 0.60 0.09 0.20 0.09 0.16 0.25 0.38 0.25 0.33 7.65 7.90 0_ 8_ INCHES MIN MAX 0.317 0.328 0.205 0.212 0.068 0.078 0.002 0.008 0.024 0.037 0.026 BSC 0.017 0.024 0.003 0.008 0.003 0.006 0.010 0.015 0.010 0.013 0.301 0.311 0_ 8_
0.076 (0.003) -T-
SEATING PLANE
C D G H
DETAIL E
Motorola Master Selection Guide
3.1-65
EEEE CCCC EEEE CCCC
-W-
TTL, ECL, CMOS and Special Logic Circuits
24-Pin Packages
DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948H-01 ISSUE O
24X K REF
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
2X
L/2
24
13
L
PIN 1 IDENT. 1 12
B -U-
0.15 (0.006) T U
S
A -V-
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 7.70 7.90 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.303 0.311 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
C 0.10 (0.004) -T- SEATING
PLANE
D
G
H
-W-
DETAIL E N K
0.25 (0.010) M
J1
J
TTL, ECL, CMOS and Special Logic Circuits
CE E CCC ECC E CCC EE
K1
N F DETAIL E
SECTION N-N
3.1-66
Motorola Master Selection Guide
28-Pin Packages
FN SUFFIX PLASTIC PLCC PACKAGE CASE 776-02 ISSUE D
B -N- Y BRK U D Z -L- -M- 0.007 (0.180)
M
0.007 (0.180)
M
T L-M
S
N
S S
T L-M
N
S
W
28 1
D
X VIEW D-D
G1
0.010 (0.250)
S
T L-M
S
N
S
V
A Z R C
0.007 (0.180) 0.007 (0.180)
M
T L-M T L-M
S
N N
S
H
0.007 (0.180)
M
T L-M
S
N
S
M
S
S
E 0.004 (0.100) G G1 0.010 (0.250)
S
K1
J
-T- VIEW S
SEATING PLANE
K F VIEW S 0.007 (0.180)
M
T L-M
S
N
S
T L-M
S
N
S
NOTES: 1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635).
DIM A B C E F G H J K R U V W X Y Z G1 K1
INCHES MIN MAX 0.485 0.495 0.485 0.495 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 --- 0.025 --- 0.450 0.456 0.450 0.456 0.042 0.048 0.042 0.048 0.042 0.056 --- 0.020 2_ 10_ 0.410 0.430 0.040 ---
MILLIMETERS MIN MAX 12.32 12.57 12.32 12.57 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 --- 0.64 --- 11.43 11.58 11.43 11.58 1.07 1.21 1.07 1.21 1.07 1.42 --- 0.50 2_ 10_ 10.42 10.92 1.02 ---
Motorola Master Selection Guide
3.1-67
TTL, ECL, CMOS and Special Logic Circuits
32-Pin Package
FA SUFFIX PLASTIC TQFP PACKAGE CASE 873A-02 ISSUE A
-T-, -U-, -Z- AE P B1
8
A A1
32 25
4X
0.20 (0.008) AB T-U Z
1
-T- B DETAIL Y
17
-U- V V1 AE
9
DETAIL Y -Z-
4X
9
S1 S
0.20 (0.008) AC T-U Z
G -AB-
SEATING PLANE
DETAIL AD
-AC-
BASE METAL
N
F
8X
D
M_ R
0.20 (0.008)
M
AC T-U Z
0.10 (0.004) AC
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -AB- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -T-, -U-, AND -Z- TO BE DETERMINED AT DATUM PLANE -AB-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -AC-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -AB-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION. MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.300 0.450 1.350 1.450 0.300 0.400 0.800 BSC 0.050 0.150 0.090 0.200 0.500 0.700 12_ REF 0.090 0.160 0.400 BSC 1_ 5_ 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF INCHES MIN MAX 0.276 BSC 0.138 BSC 0.276 BSC 0.138 BSC 0.055 0.063 0.012 0.018 0.053 0.057 0.012 0.016 0.031 BSC 0.002 0.006 0.004 0.008 0.020 0.028 12_ REF 0.004 0.006 0.016 BSC 1_ 5_ 0.006 0.010 0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF
CE
SECTION AE-AE
X DETAIL AD
TTL, ECL, CMOS and Special Logic Circuits
GAUGE PLANE
0.250 (0.010)
H
W
K
Q_
3.1-68
EE EE EE
J
DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X
Motorola Master Selection Guide
40-Pin Packages
N SUFFIX PLASTIC DIP PACKAGE CASE 711-03 ISSUE C
40
21
B
1 20
NOTES: 1. POSITIONAL TOLERANCE OF LEADS (D), SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
A N
L C
DIM A B C D F G H J K L M N MILLIMETERS MIN MAX 51.69 52.45 13.72 14.22 3.94 5.08 0.36 0.56 1.02 1.52 2.54 BSC 1.65 2.16 0.20 0.38 2.92 3.43 15.24 BSC 0_ 15_ 0.51 1.02 INCHES MIN MAX 2.035 2.065 0.540 0.560 0.155 0.200 0.014 0.022 0.040 0.060 0.100 BSC 0.065 0.085 0.008 0.015 0.115 0.135 0.600 BSC 0_ 15_ 0.020 0.040
J H G F D K
SEATING PLANE
M
48-Pin Packages
J SUFFIX CERAMIC DIP PACKAGE CASE 740-03 ISSUE B
-A-
48 25
-B-
1 24
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. DIM A B C D E F G J K L M N 48 PL INCHES MIN MAX 2.376 2.424 0.576 0.604 0.120 0.127 0.015 0.021 0.050 BSC 0.030 0.055 0.100 BSC 0.008 0.013 0.100 0.165 0.600 BSC 0 10 0.040 0.060 M MILLIMETERS MIN MAX 60.36 61.56 14.64 15.34 3.05 4.31 0.381 0.533 1.27 BSC 0.762 1.397 2.54 BSC 0.204 0.330 2.54 4.19 15.24 BSC 0 10 1.016 1.524
N -T-
SEATING PLANE
C
L
K F D
48 PL
E G 0.25 (0.010)
M
M J
TA
M
0.25 (0.010)
M
TB
Motorola Master Selection Guide
3.1-69
TTL, ECL, CMOS and Special Logic Circuits
48-Pin Packages
N SUFFIX PLASTIC DIP PACKAGE CASE 767-02 ISSUE B
-A-
48 25 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH. MAXIMUM MOLD FLASH 0.25 (0.010). INCHES MIN MAX 2.415 2.445 0.540 0.560 0.155 0.200 0.014 0.022 0.040 0.060 0.100 BSC 0.070 BSC 0.008 0.015 0.115 0.150 0.600 BSC 0_ 15_ 0.020 0.040 MILLIMETERS MIN MAX 61.34 62.10 13.72 14.22 3.94 5.08 0.36 0.55 1.02 1.52 2.54 BSC 1.79 BSC 0.20 0.38 2.92 3.81 15.24 BSC 0_ 15_ 0.51 1.01
-B-
1 24
TIP TAPER
DETAIL X
C
L
-T-
SEATING PLANE
K DETAIL X F D 32 PL 0.51 (0.020) G
M
N J
48 PL M
M 48 PL
TA
S
0.25 (0.010)
TB
S
DIM A B C D F G H J K L M N
DT SUFFIX PLASTIC TSSOP PACKAGE CASE 1201-01 ISSUE A
48X
K REF 0.12 (0.005)
M
TU
S
V
S
K K1 J J1
48
25
M
SECTION N-N L B -U- N
1 24
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 5. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 6. DIMENSIONS A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 12.40 12.60 6.00 6.20 --- 1.10 0.05 0.15 0.50 0.75 0.50 BSC 0.37 --- 0.09 0.20 0.09 0.16 0.17 0.27 0.17 0.23 7.95 8.25 0_ 8_ INCHES MIN MAX 0.488 0.496 0.236 0.244 --- 0.043 0.002 0.006 0.020 0.030 0.0197 BSC 0.015 --- 0.004 0.008 0.004 0.006 0.007 0.011 0.007 0.009 0.313 0.325 0_ 8_
0.254 (0.010)
PIN 1 IDENT.
A -V-
N F DETAIL E M 0.25 (0.010)
D 0.076 (0.003) -T- SEATING
PLANE
C DETAIL E G H
TTL, ECL, CMOS and Special Logic Circuits
3.1-70
EEE CCC EEE CCC
TU
S
-W-
Motorola Master Selection Guide
52-Pin Packages
FN SUFFIX PLASTIC PLCC PACKAGE CASE 778-02 ISSUE C
B -N- Y BRK D Z -L- -M-
0.007 (0.18) U
M
T L-M
M
S
N
S S
0.007 (0.18)
T L-M
N
S
W D
52 1
X V VIEW D-D 0.007 (0.18) 0.007 (0.18)
M
G1 0.010 (0.25)
S
T L-M
S
N
S
A Z R
T L-M T L-M
S
N N
S
M
S
S
E C G G1 0.010 (0.25)
S
J VIEW S T L-M N
0.004 (0.100) -T- SEATING
PLANE
S
S
H K1
0.007 (0.18)
M
T L-M
S
N
S
NOTES: 1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). INCHES MIN MAX 0.785 0.795 0.785 0.795 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 --- 0.025 --- 0.750 0.756 0.750 0.756 0.042 0.048 0.042 0.048 0.042 0.056 --- 0.020 2_ 10 _ 0.710 0.730 0.040 --- MILLIMETERS MIN MAX 19.94 20.19 19.94 20.19 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 --- 0.64 --- 19.05 19.20 19.05 19.20 1.07 1.21 1.07 1.21 1.07 1.42 --- 0.50 2_ 10 _ 18.04 18.54 1.02 ---
K VIEW S
F
0.007 (0.18)
M
T L-M
S
N
S
DIM A B C E F G H J K R U V W X Y Z G1 K1
Motorola Master Selection Guide
3.1-71
TTL, ECL, CMOS and Special Logic Circuits
52-Pin Packages
FA SUFFIX PLASTIC TQFP PACKAGE CASE 848D-03 ISSUE D
4X 4X 13 TIPS
0.20 (0.008) H L-M N
0.20 (0.008) T L-M N -X- X=L, M, N
52 1
40 39
C L AB G
3X
VIEW Y -M- B V AB VIEW Y F
BASE METAL
-L-
B1
13 14 26 27
V1
PLATING
J
A1 S1 A S
-N-
0.13 (0.005)
SECTION AB-AB
ROTATED 90_ CLOCKWISE
C -H- -T-
SEATING PLANE
4X
q2
0.10 (0.004) T
4X
q3
VIEW AA
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -L-, -M- AND -N- TO BE DETERMINED AT DATUM PLANE -H-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -T-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.46 (0.018). MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR PROTRUSION 0.07 (0.003). MILLIMETERS MIN MAX 10.00 BSC 5.00 BSC 10.00 BSC 5.00 BSC --- 1.70 0.05 0.20 1.30 1.50 0.20 0.40 0.45 0.75 0.22 0.35 0.65 BSC 0.07 0.20 0.50 REF 0.08 0.20 12.00 BSC 6.00 BSC 0.09 0.16 12.00 BSC 6.00 BSC 0.20 REF 1.00 REF 0_ 7_ --- 0_ 12 _ REF 12 _ REF INCHES MIN MAX 0.394 BSC 0.197 BSC 0.394 BSC 0.197 BSC --- 0.067 0.002 0.008 0.051 0.059 0.008 0.016 0.018 0.030 0.009 0.014 0.026 BSC 0.003 0.008 0.020 REF 0.003 0.008 0.472 BSC 0.236 BSC 0.004 0.006 0.472 BSC 0.236 BSC 0.008 REF 0.039 REF 0_ 7_ --- 0_ 12 _ REF 12 _ REF
0.05 (0.002)
S
W
q1
C2
2X R
R1
0.25 (0.010)
q
GAGE PLANE
K C1 E VIEW AA Z
DIM A A1 B B1 C C1 C2 D E F G J K R1 S S1 U V V1 W Z 1 2 3
TTL, ECL, CMOS and Special Logic Circuits
3.1-72
CCCC EEEE CCCC EEEE
M
U
D T L-M
S
N
S
Motorola Master Selection Guide
56-Pin Packages
DT SUFFIX PLASTIC TSSOP PACKAGE CASE 1202-01 ISSUE A
56X
K REF 0.12 (0.005)
M
TU
S
V
S
K K1 J J1
56
29
0.254 (0.010)
L
B -U-
1 28
SECTION N-N
N
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 5. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 6. DIMENSIONS A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 13.90 14.10 6.00 6.20 --- 1.10 0.05 0.15 0.50 0.75 0.50 BSC 0.12 --- 0.09 0.20 0.09 0.16 0.17 0.27 0.17 0.23 7.95 8.25 0_ 8_ INCHES MIN MAX 0.547 0.555 0.236 0.244 --- 0.043 0.002 0.006 0.020 0.030 0.0197 BSC 0.005 --- 0.004 0.008 0.004 0.006 0.007 0.011 0.007 0.009 0.313 0.325 0_ 8_
PIN 1 IDENT.
A -V- N F DETAIL E M 0.25 (0.010)
D 0.076 (0.003) -T- SEATING
PLANE
C DETAIL E G H
Motorola Master Selection Guide
3.1-73
CCCC EE CCCC EE
M
TU
S
-W-
TTL, ECL, CMOS and Special Logic Circuits
68-Pin Package
FN SUFFIX PLASTIC PLCC PACKAGE CASE 779-02 ISSUE C
B -N- Y BRK D U
0.007 (0.18)
M
T L-M
M
S
N
S
S
0.007 (0.18)
T L-M
N
S
Z -L- -M-
W D V X VIEW D-D G1 0.010 (0.25)
68
1
S
T L-M
S
N
S
A
0.007 (0.18)
M
T L-M
S
N
S
Z
R
0.007 (0.18)
M
T L-M
S
N
S
E C G G1 0.010 (0.25)
S
0.004 (0.10) J VIEW S T L-M
S
-T-
SEATING PLANE
N
S
NOTES: 1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). DIM A B C E F G H J K R U V W X Y Z G1 K1 INCHES MIN MAX 0.985 0.995 0.985 0.995 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 --- 0.025 --- 0.950 0.956 0.950 0.956 0.042 0.048 0.042 0.048 0.042 0.056 --- 0.020 2_ 10_ 0.910 0.930 0.040 --- MILLIMETERS MIN MAX 25.02 25.27 25.02 25.27 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 --- 0.64 --- 24.13 24.28 24.13 24.28 1.07 1.21 1.07 1.21 1.07 1.42 --- 0.50 2_ 10_ 23.12 23.62 1.02 ---
H
0.007 (0.18)
M
T L-M
S
N
S
K1
K F VIEW S 0.007 (0.18)
M
T L-M
S
N
S
TTL, ECL, CMOS and Special Logic Circuits
3.1-74
Motorola Master Selection Guide
Programmable Array 84-Pin Package
FN SUFFIX PLASTIC PLCC PACKAGE CASE 780A-01 ISSUE A
B 0.18 (0.007) U -N- 0.18 (0.007) Y BRK D Z1
M M
TN
S
-P
S
L
S
S
-M
S
S
TN
-P
L
S
-M
S
-L-
-M-
W D
84 1
-P-
V
X 0.25 (0.010)
M
G1 TN
S
-P
S
L
S
-M
S
DETAIL D-D A 0.18 (0.007) Z 0.18 (0.007)
M M
TL R TL
S
-M
S
N
S
-P
S
S
-M
S
N
S
-P
S
E C G G1 0.25 (0.010)
S
J
S
0.100 (0.004) -T- SEATING
PLANE
TL
-M
S
N
S
-P
S
DETAIL S
0.18 (0.007) H 0.18 (0.007)
M M
TL TN
S S
-M -P
S S
N L
S S
-P -M
S S
K1 K DETAIL S F
0.18 (0.007) 0.18 (0.007)
M M
TL TN
S S
-M -P
S S
N L
S S
-P -M
S S
NOTES: 1. DATUMS -L-, -M-, -N-, AND -P- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PACKAGE BODY AT GLASS PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE GLASS PROTRUSION. ALLOWABLE GLASS PROTRUSION IS 0.25 (0.010) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. INCHES MILLIMETERS DIM MIN MAX MIN MAX A 1.185 1.195 30.10 30.35 B 1.185 1.195 30.10 30.35 C 0.165 0.180 4.20 4.57 E 0.090 0.110 2.29 2.79 F 0.013 0.021 0.33 0.53 G 0.050 BSC 1.27 BSC H 0.026 0.032 0.66 0.81 J 0.020 --- 0.51 --- K 0.025 --- 0.64 --- R 1.150 1.156 29.21 29.36 U 1.150 1.156 29.21 29.36 V 0.042 0.048 1.07 1.21 W 0.042 0.048 1.07 1.21 X 0.042 0.056 1.07 1.42 Y --- 0.020 --- 0.50 Z 2_ 10_ 2_ 10_ G1 1.110 1.130 28.20 28.70 K1 0.040 --- 1.02 --- Z1 2_ 10_ 2_ 10_
Motorola Master Selection Guide
3.1-75
TTL, ECL, CMOS and Special Logic Circuits
Programmable Array 128-Pin Package
DD SUFFIX PLASTIC QFP PACKAGE CASE 862A-02 ISSUE B
L Y
96 97 65
64 S S
S
H A-B
-A- L
-B- B
0.05 (0.002) D
M
M
V
C A-B
S
D
P
D
-A-, -B-, -D- DETAIL A
0.20 (0.008)
DETAIL A Z
128 33
0.20 (0.008)
1
-D- A 0.20 (0.008)
M
32
H A-B
S
D
S
0.05 (0.002) A-B S 0.20 (0.008)
M
C A-B
S
D
S
M CE -C-
SEATING PLANE
DETAIL C -H-
DATUM PLANE
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER 3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -A-, -B- AND -D-TO BE DETERMINED AT DATUM PLANE -H-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -C-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OF THE FOOT. MILLIMETERS MIN MAX 27.90 28.10 27.90 28.10 --- 4.07 0.30 0.45 3.17 3.67 0.30 0.40 0.80 BSC 0.25 0.35 0.13 0.23 0.65 0.95 24.80 REF 5_ 16 _ 0.13 0.17 0.40 BSC 0_ 7_ 0.13 0.30 30.95 31.45 0.13 --- 0_ --- 30.95 31.45 0.40 --- 1.60 REF 1.60 REF 1.60 REF INCHES MIN MAX 1.098 1.106 1.098 1.106 --- 0.160 0.012 0.018 0.125 0.144 0.012 0.016 0.032 BSC 0.010 0.014 0.005 0.009 0.026 0.037 0.976 REF 5_ 16 _ 0.005 0.007 0.016 BSC 0_ 7_ 0.005 0.012 1.219 1.238 0.005 --- 0_ --- 1.219 1.238 0.016 --- 0.063 REF 0.063 REF 0.063 REF
G DETAIL B H
0.10 (0.004) M
F J
W U N
BASE METAL S DATUM PLANE
-H-
T R K Q
D
0.20 (0.008)
M
C A-B
D
S
X DETAIL C
DETAIL B
DIM A B C D E F G H J K L M N P Q R S T U V W X Y Z
TTL, ECL, CMOS and Special Logic Circuits
EEEE EEEE EEEE
3.1-76
Motorola Master Selection Guide
Programmable Array 160-Pin Package
DH SUFFIX PLASTIC QFP PACKAGE CASE 864A-03 ISSUE C
Y
120
L
81
121
80
S
D
D
S
-A-, -B-, -D-
S
H A-B
0.20 (0.008) A-B
-A- L
-B- B
C A-B
S
B
B
M
0.20 (0.008)
0.20 (0.008)
V
M
P G DETAIL A
DETAIL A
160
41
Z
1
-D- A 0.20 (0.008)
M
40
0.20 (0.008) A-B S 0.20 (0.008)
M
N C A-B
S
D
S
DETAIL C
-H-
0.13 (0.005)
M_
TOP & BOTTOM NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -A-, -B- AND -D- TO BE DETERMINED AT DATUM PLANE -H-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -C-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT.
U_ C E -H-
T R Q_
-C-
SEATING PLANE
W H X 0.10 (0.004) DETAIL C K
Motorola Master Selection Guide
3.1-77
TTL, ECL, CMOS and Special Logic Circuits
CCCC EEEE CCCC EEEE CCCC
F D
M
H A-B
S
D
S
BASE METAL
J
C A-B
S
D
S
SECTION B-B
DIM A B C D E F G H J K L M N P Q R S T U V W X Y Z
MILLIMETERS MIN MAX 27.90 28.10 27.90 28.10 3.35 3.85 0.22 0.38 3.20 3.50 0.22 0.33 0.65 BSC 0.25 0.35 0.11 0.23 0.70 0.90 25.35 REF 5_ 16_ 0.11 0.19 0.325 BSC 0_ 7_ 0.13 0.30 31.00 31.40 0.13 --- 0_ --- 31.00 31.40 0.40 --- 1.60 REF 1.33 REF 1.33 REF
INCHES MIN MAX 1.098 1.106 1.098 1.106 0.132 0.152 0.009 0.015 0.126 0.138 0.009 0.013 0.026 REF 0.010 0.014 0.004 0.009 0.028 0.035 0.998 REF 5_ 16_ 0.004 0.007 0.013 BSC 0_ 7_ 0.005 0.012 1.220 1.236 0.005 --- 0_ --- 1.220 1.236 0.016 --- 0.063 REF 0.052 REF 0.052 REF
Programmable Array 181-Pin Package
HI SUFFIX CERAMIC PGA PACKAGE CASE 768N-01 ISSUE O
A
PIN 1 INDENTIFICATION
K C F
A B C D E F G H J K L M N P R 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
G
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH.
G
DIM A B C D F G K L M N
B
M
N L
SEATING PLANE
INCHES MIN MAX 1.555 1.595 1.555 1.595 0.102 0.124 0.016 0.020 0.040 0.060 0.100 BSC 0.110 0.150 0.043 0.057 0.655 0.675 0.090 0.110
MILLIMETERS MIN MAX 39.50 40.51 39.50 40.51 2.59 3.15 0.41 0.51 1.02 1.52 2.54 BSC 2.79 3.81 1.09 1.45 16.64 17.15 2.29 2.79
D 181 PL -T- 0.030 (0.76) 0.015 (0.38)
M M
TA T
S
B
S
TTL, ECL, CMOS and Special Logic Circuits
3.1-78
Motorola Master Selection Guide
Programmable Array 208-Pin Package
DK SUFFIX PLASTIC QFP PACKAGE CASE 872A-01 ISSUE O
L Y
156 157 105 104 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -A-, -B- AND -D- TO BE DETERMINED AT DATUM PLANE -H-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -C-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.38 (0.015). DIM A B C D E F G H J K L M N P Q R S T U V W X Y Z MILLIMETERS MIN MAX 27.90 28.10 27.90 28.10 3.45 4.10 0.14 0.30 3.20 3.60 0.14 0.26 0.50 BSC 0.25 0.35 0.09 0.20 0.70 0.90 25.50 REF 5_ 9_ 0.09 0.18 0.25 BSC 0_ 7_ 0.13 0.30 31.00 31.40 0.13 --- 0_ --- 31.00 31.40 0.40 --- 1.60 REF 1.25 REF 1.25 REF INCHES MIN MAX 1.098 1.106 1.098 1.106 0.136 0.161 0.005 0.012 1.126 0.142 0.005 0.010 0.020 BSC 0.010 0.014 0.003 0.008 0.027 0.036 1.004 REF 5_ 9_ 0.003 0.007 0.010 BSC 0_ 7_ 0.005 0.012 1.220 1.236 0.005 --- 0_ --- 1.220 1.236 0.016 --- 0.063 REF 0.049 REF 0.049 REF
S
D
S
H A-B
-A- L -B- DETAIL A B
0.05 (0.002) A-B
V
M
0.20 (0.008)
208 1 52
53
Z
-D- A 0.20 (0.008)
M
H A-B
S
D
S
0.05 (0.002) A-B S 0.20 (0.008) E C -H- -C-
SEATING PLANE DATUM PLANE M
C A-B
S
D
S
M
DETAIL C
H
G DETAIL B
0.10 (0.004) M U
BASE METAL
0.20 (0.008)
M
C A-B
S
D
S
T
P F -H- N
DATUM PLANE
-A-, -B-, -D-
0.06 (0.002)
DETAIL A
Motorola Master Selection Guide
CCCCC EEEE CEEE E CCCCC ECCCC EEE
J D
M
R B W K X DETAIL C
C A-B
S
D
S
B Q
DETAIL B SECTION B-B ROTATED 7 _ CCW
3.1-79
TTL, ECL, CMOS and Special Logic Circuits
Programmable Array 224-Pin Package
KE SUFFIX PIN GRID ARRAY PACKAGE CASE 860F-01 ISSUE O
C 16X 0.100 B A Q
SEATING PLANE A B C D E F G H J K L M N P R T U 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0.080 MAX
D
E
A
L
224X
0.020 0.016 0.030 0.010
M M
0.008 C
CA C
M
B
M
NOTES: 1. DIMENSIONS ARE IN INCHES. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. MINIMUM SPACING BETWEEN CONDUCTORS SHALL BE 0.020. DIM A D E L Q INCHES MIN MAX 0.070 0.145 1.740 1.780 1.740 1.780 0.100 0.200 0.045 0.075
TTL, ECL, CMOS and Special Logic Circuits
3.1-80
Motorola Master Selection Guide
16X 0.100
0.080 MAX
Programmable Array 256-Pin Package
BG SUFFIX PLASTIC BGA PACKAGE CASE 1208A-01 ISSUE O
X
D F
DETAIL K M
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSION b IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER, PARALLEL TO DATUM PLANE Z. 4. DATUM Z (SEATING PLANE) IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. MILLIMETERS MIN MAX 1.92 2.32 0.50 0.70 0.36 REF 1.12 1.22 0.60 0.90 27.00 BSC 27.00 BSC 24.00 24.70 24.00 24.70 1.27 BSC 0.635 BSC
E
G
M Y 0.20 S
20X
DIM A A1 A2 A3 b D E F G e S
e
21 20 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y
A3
e
A
0.35 Z
20X
A2
A1
Z
S
4
0.15 Z
ROTATED 90 _CLOCKWISE
DETAIL K
3
256X
b VIEW M-M
0.25 Z X Y
Motorola Master Selection Guide
3.1-81
TTL, ECL, CMOS and Special Logic Circuits
Programmable Array 299-Pin Package
HV SUFFIX PIN GRID ARRAY PACKAGE CASE 861B-01 ISSUE O
C 16X 0.100 B A Q
SEATING PLANE A B C D E F G H J K L M N P R T U V W Y 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0.080 MAX
D
E
A
L
224X
0.020 0.016 0.030 0.010
M M
0.008 C
CA C
M
B
M
NOTES: 1. DIMENSIONS ARE IN INCHES. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. MINIMUM SPACING BETWEEN CONDUCTORS SHALL BE 0.020. DIM A D E L Q S INCHES MIN MAX 0.070 0.145 2.040 2.080 2.040 2.080 0.100 0.200 0.045 0.075 0.050 BSC
TTL, ECL, CMOS and Special Logic Circuits
3.1-82
Motorola Master Selection Guide
16X 0.100
0.080 MAX
Packaging Information
Surface Mount
Why Surface Mount?
Surface Mount Technology is utilized to offer answers to many problems that have been created in the use of insertion technology. Limitations have been reached with insertion packages and PC board technology. Surface Mount Technology offers the opportunity to continue to advance the state- of-the-art designs that cannot be accomplished with Insertion Technology. Surface Mount Packages allow more optimum device performance with the smaller Surface Mount configuration. Internal lead lengths, parasitic capacitance and inductance that placed limitations on chip performance have been reduced. The lower profile of Surface Mount Packages allows more boards to be utilized in a given amount of space. They are stacked closer together and utilize less total volume than insertion populated PC boards. Printed circuit costs are lowered with the reduction of the number of board layers required. The elimination or reduction of the number of plated through holes in the board, contributes significantly to lower PC board prices. Automatic placement equipment is available that can place Surface Mount components at the rate of a few thousand per hour to hundreds of thousands of components per hour. Surface Mount Technology is cost effective, allowing the manufacturer the opportunity to produce smaller units and/or offer increased functions with the same size product. Surface Mount assembly does not require the preparation of components that are common on insertion technology lines. Surface Mount components are sent directly to the assembly line, eliminating an intermediate step.
Pin Conversion Tables
Dual-in-Line Package to PLCC Pin Conversion Data
The following table gives the equivalent I/O pinouts of Dual-In-Line Package (DIP) configuration and Plastic Leaded Chip Carrier (PLCC) packages.* Conversion Tables
8 PIN DIP 20 PIN PLCC 1 2 2 5 3 7 4 10 5 12 6 15 7 17 8 20
14 PIN DIP 20 PIN PLCC
1 2
2 3
3 4
4 6
5 8
6 9
7 10
8 12
9 13
10 14
11 16
12 18
13 19
14 20
16 PIN DIP 20 PIN PLCC
1 2
2 3
3 4
4 5
5 7
6 8
7 9
8 10
9 12
10 13
11 14
12 15
13 17
14 18
15 19
16 20
20 PIN DIP 20 PIN PLCC
1 1
2 2
3 3
4 4
5 5
6 6
7 7
8 8
9 9
10 10
11 11
12 12
13 13
14 14
15 15
16 16
17 17
18 18
19 19
20 20
24 PIN DIP 28 PIN PLCC
1 2
2 3
3 4
4 5
5 6
6 7
7 9
8 10
9 11
10 12
11 13
12 14
13 16
14 17
15 18
16 19
17 20
18 21
19 23
20 24
21 25
22 26
23 27
24 28
* The MC1648 has a Non-Standard Conversion Table. For more information, refer to the Motorola MECL Data Book, DL122/D.
Motorola Master Selection Guide
3.1-83
TTL, ECL, CMOS and Special Logic Circuits
Tape and Reel
Logic Integrated Circuits
Motorola's tape and reel packaging fully conforms to the latest EIA RS-481A specification. The antistatic embossed tape provides a secure cavity sealed with a peel-back cover tape. Mechanical Polarization
Typical
PLCC Devices
PIN 1
View from tape side
Linear direction of travel Typical
SOIC Devices
View from tape side
Linear direction of travel
General Information
-- Reel Size -- Tape Width 13 inch (330 mm) Suffix: R2 12 mm to 24 mm (see table) -- Units/Reel 500 to 5000 (see table)
Ordering Information
To order devices which are to be delivered in Tape and Reel, add the suffix R2 to the device number being ordered.
Tape and Reel Data
Device Type PLCC-20 PLCC-28 SO-8 SO-14 SO-16 SO-16 Wide SO-20 Wide Tape Width (mm) 16 24 12 16 16 16 24 Device/Reel 1,000 500 2,500 2,500 2,500 1,000 1,000 Reel Size (inch) 13 13 13 13 13 13 13 Min Lot Size Per Part No. Tape and Reel 3,000 500 5,000 5,000 5,000 5,000 5,000
TTL, ECL, CMOS and Special Logic Circuits
3.1-84
Motorola Master Selection Guide

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